Interrupt Sources And Priorities - Intel 8XC196K Series User Manual

8XC196K x , J x , CA USER'S MANUAL
Table 5-2. Interrupt and PTS Control and Status Registers (Continued)
Register Register
Mnemonic Name
EPA_MASK EPA
Interrupt
EPA_MASK1
Mask
Registers
EPA_PEND EPA
Interrupt
EPA_PEND1
Pending
Registers
EPAIPV EPA
Interrupt
Priority
Vector
INT_MASK Interrupt
Mask
INT_MASK1
Registers
INT_PEND Interrupt
Pending
INT_PEND1
Registers
PSW Program
Status Word
PTSSEL PTS Select
Register
PTSSRV PTS
Service
Register
5.3

INTERRUPT SOURCES AND PRIORITIES

Table 5-3 lists the interrupts sources, their default priorities (30 is highest and 0 is lowest), and
their vector addresses. The unimplemented opcode and software trap interrupts are not priori-
tized; they go directly to the interrupt controller for servicing. The priority encoder determines
the priority of all other pending interrupt requests. NMI has the highest priority of all prioritized
interrupts, PTS interrupts have the next highest priority, and standard interrupts have the lowest.
The priority encoder selects the highest priority pending request and the interrupt controller se-
lects the corresponding vector location in special-purpose memory. This vector contains the start-
ing (base) address of the corresponding PTS control block (PTSCB) or interrupt service routine.
PTSCBs must be located in register RAM on a quad-word boundary.
5-4
These registers enable/disable the 20 multiplexed EPA interrupts
The bits in these registers are set by hardware to indicate that a
multiplexed EPA interrupt is pending.
This register contains a number from 00H to 14H corresponding to the
highest-priority pending EPA x interrupt source. This value allows
software to branch via the TIJMP instruction to the correct interrupt
service routine when the EPAx interrupt is activated. Reading this
register clears the pending bit of the associated interrupt source. The
EPA x pending bit (INT_PEND.7) is cleared when all the pending bits
for its sources (in EPA_PEND and EPA_PEND1) have been cleared.
These registers enable/disable each maskable interrupt (that is, each
interrupt except unimplemented opcode, software trap, and NMI.)
The bits in this register are set by hardware to indicate that an interrupt
is pending.
This register contains one bit that globally enables or disables servicing
of all maskable interrupts and another that enables or disables the
PTS. These bits are set or cleared by executing the enable interrupts
(EI), disable interrupts (DI), enable PTS (EPTS), and disable PTS
(DPTS) instructions.
This register selects either a PTS routine or a standard interrupt
service routine for each of the maskable interrupt requests.
The bits in this register are set by hardware to request an end-of-PTS
interrupt.
Description