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P6.4–P6.7
6.3.5
Design Considerations for External Interrupt Inputs
To configure a port pin that serves as an external interrupt input, you must set the corresponding
bits in the configuration registers (Px_DIR, Px_MODE, and Px_REG). To configure
P2.2/EXTINT as an external interrupt input, we recommend the following sequence to prevent a
false interrupt request:
1.
Disable interrupts by executing the DI instruction.
2.
Set the Px_DIR bit.
3.
Set the Px_MODE bit.
4.
Set the Px_REG bit.
5.
Clear the INT_PEND and INT_PEND1 bits.
6.
Enable interrupts (optional) by executing the EI instruction.
6.4
BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS)
Ports 3 and 4 are eight-bit, bidirectional, memory-mapped I/O ports. They can be addressed only
with indirect or indexed addressing and cannot be windowed. Ports 3 and 4 provide the multi-
plexed address/data bus. In programming modes, ports 3 and 4 serve as the programming bus
(PBUS). Port 3 can also serve as the slave port (8XC196Kx only). Port 5 supplies the bus-control
signals.
During external memory bus cycles, the processor takes control of ports 3 and 4 and automatical-
ly configures them as complementary output ports for driving address/data or as inputs for read-
ing data. For this reason, these ports have no mode registers.
Systems with EA# tied inactive do not use the address/data bus, and systems that do use the ad-
dress/data bus have idle time between external bus cycles. When the address/data bus is not in
use, you can use the ports for I/O. Like port 5, these ports use standard CMOS input buffers. How-
ever, ports 3 and 4 must be configured entirely as complementary or open-drain ports; their pins
cannot be configured individually. Systems with EA# tied active cannot use ports 3 and 4 as stan-
dard I/O; when EA# is active, these ports will function only as the address/data bus.
A value written to any of the upper four bits of P6_REG (bits 4–7) is
held in a buffer until the corresponding P6_MODE bit is cleared, at
which time the value is loaded into the P6_REG bit. A value read
from a P6_REG bit is the value currently in the register, not the value
in the buffer. Therefore, any change to a P6_REG bit can be read
only after the corresponding P6_MODE bit is cleared.
I/O PORTS
6-15
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