Intel 8XC196K Series User Manual page 566

EPA_PEND1
When hardware detects a pending EPA x interrupt, it sets the corresponding bit in EPA interrupt
pending (EPA_PEND or EPA_PEND1) registers. The EPAIPV register contains a number that
identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA
interrupt pending bit associated with the EPAIPV priority value is cleared.
7
— —
Bit
Number
7:4 Reserved; always write as zeros.
3:0 Any set bit indicates that the corresponding EPA x interrupt source is pending. The bit is
cleared when the EPA interrupt priority vector register (EPAIPV) is read.
— — COMP0
Function
REGISTERS
EPA_PEND1
Address:
Reset State:
COMP1 OVRTM1 OVRTM2
1FA6H
00H
0
C-39