Intel 8XC196K Series User Manual page 204

Table 9-2. Slave Port Control and Status Registers (Continued)
Mnemonic Address
INT_PEND1 12H
P3_PIN 1FFEH
P3_REG 1FFCH
SLP_CMD 1FFAH
SLP_CON 1FFBH
SLP_STAT 1FF8H
Interrupt Pending 1
Bit 0, when set, indicates a pending command buffer full (CBF) interrupt.
This bit is set after the master writes to the command register,
SLP_CMD.
Slave Port Data Input Register
This register is also used for standard port 3 operation.
In slave port operation, this register accepts data written by the master
to be read by the slave. The slave can only read from this register and
the master can only write to it. If the master attempts to read from
P3_PIN, it will actually read P3_REG.
To write to this register in standard slave mode, the master must first
write "0" to the pin selected by SLP_CON.2. To write to this register in
shared memory mode (8XC196KS and KT only), the master must first
write "0" to the SLP1 pin.
Slave Port Data Output Register
This register is also used for standard port 3 operation.
In slave port operation, this register accepts data written by the slave to
be read by the master. The slave can write to and read from this register.
The master can only read it. If the master attempts to write to this
register, it will actually write to P3_PIN.
To read from this register in standard slave mode, the master must first
write "0" to the pin selected by SLP_CON.2. To read from this register in
shared memory mode (8XC196KS and KT only), the master must first
write "0" to the SLP1 pin.
Slave Port Command Register
This register accepts commands from the master to the slave. The
commands are defined by the device software. The slave can read from
and write to this register. The master can only write to it.
To write to this register in standard slave mode, the master must first
write "1" to the pin selected by SLP_CON.2. To write to this register in
shared memory mode (8XC196KS and KT only), the master must first
write "1" to the SLP1 pin.
Slave Port Control Register
This register is used to configure the slave port. It selects the operating
mode (8XC196KS and KT only), enables and disables slave port
operation, controls whether the master accesses the data registers or
the control and status registers, and controls whether the SLPINT signal
is asserted when the input buffer empty (IBE) and output buffer full
(OBF) flags are set in the SLP_STAT register. Only the slave can access
this register.
Slave Port Status Register
The master can read this register to determine the status of the slave.
The slave can read all bits. If the master attempts to write to SLP_STAT,
it actually writes to SLP_CMD. To read from this register in standard
slave mode, the master must first write "1" to the pin selected by
SLP_CON.2. To read from this register in shared memory mode
(8XC196KS and KT only), the master must first write "1" to the SLP1
pin.
Description
SLAVE PORT
9-5