Intel 8XC196K Series User Manual page 222

Port Pin EPA Signal(s)
P1.0 EPA0
T2CLK
P1.1 EPA1
P1.2 EPA2
T2DIR
P1.3 EPA3
†
P1.7:4 EPA7:4
P6.0 EPA8
COMP0
P6.1 EPA9
COMP1
†
P6.2 T1CLK
†
P6.3 T1DIR
†
This pin is not implemented on the 8XC196J x and 87C196CA devices.
Mnemonic Address
COMP0_CON 1F88H
COMP1_CON 1F8CH
COMP0_TIME 1F8AH
COMP1_TIME 1F8EH
EPA_MASK 1FA0H
EPA_MASK1 1FA4H
EPA_PEND 1FA2H
Table 10-2. EPA and Timer/Counter Signals
EPA
Signal Type
I/O
I
I/O
I/O
I
I/O
I/O
I/O
O
I/O
O
I
I
Table 10-3. EPA Control and Status Registers
EPA x Compare Control
These registers control the functions of the compare-only
channels.
EPA x Compare Time
These registers contain the time at which an event is to occur on
the compare-only channels.
EPA Interrupt Mask
The bits in this 16-bit register enable and disable (mask) 16 of the
interrupts associated with the EPA x interrupt, EPA4–9 and
OVR0–9.
EPA Interrupt Mask 1
The bits in this 8-bit register enable and disable (mask) four
interrupts associated with the EPA x interrupt, OVRTM1,
OVRTM2, COMP0, and COMP1
EPA Interrupt Pending
Any set bit in this register indicates a pending interrupt.
EVENT PROCESSOR ARRAY (EPA)
Description
High-speed input/output for capture/compare
channel 0.
External clock source for timer 2. If you use
T2CLK, you cannot use capture/compare channel
0.
High-speed input/output for capture/compare
channel 1.
High-speed input/output for capture/compare
channel 2.
External direction control for timer 2. If you use
T2DIR, you cannot use capture/compare channel
2.
High-speed input/output for capture/compare
channel 3.
High-speed input/output for capture/compare
channels 4–7.
High-speed input/output for capture/compare
channel 8.
Output of the compare-only channel 0.
High-speed input/output for capture/compare
channel 9.
Output of the compare-only channel 1.
External clock source for timer 1.
External direction control for timer 1.
Description
10-3