Table of Contents
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Port 3
addressing, 6-15
configuration, 6-18
configuring for slave port, 9-14
idle, powerdown, reset status, B-20, B-21,
B-22
operation, 6-16–6-18
overview, 6-1
pin configuration, 6-12, 6-15
structure, 6-17
Port 4
addressing, 6-15
configuration, 6-18
idle, powerdown, reset status, B-20, B-21,
B-23
operation, 6-16–6-18
overview, 6-1
pin configuration, 6-12, 6-15
structure, 6-17
Port 5, B-14
configuring for slave port, 9-14
considerations, 6-13
idle, powerdown, reset status, B-20
initializing, 6-10
logic tables, 6-9
operation, 6-4, 6-9, 6-13
overview, 6-1
pin configuration, 6-10, 6-12, 6-13
example, 6-11
SFRs, 6-5, 6-6, 10-4, 14-2
structure, 6-8
Port 6, B-15
considerations, 6-14
initializing, 6-10
logic tables, 6-9
operation, 6-4
overview, 6-1
pin configuration, 6-10, 6-12
example, 6-11
SFRs, 6-5, 6-6, 10-4, 10-5
structure, 6-8
Port, serial‚ See SIO port
Port, slave‚ See slave port
Port, synchronous serial, See SSIO port
Ports, 2-9
Power and ground pins
minimum hardware connections, 13-5
Power consumption, reducing, 2-12, 14-4
Powerdown mode, 2-11, 2-12, 14-4–14-7
circuitry
external, 14-7, 14-8
disabling, 14-4
entering, 14-5
exiting with EXTINT, 14-6–14-9
exiting with V
, 14-5
PP
pin status, B-20, B-21, B-22
Powerdown sequence, programming modes, 16-15
Power-up sequence, programming modes, 16-15
Prefetch queue, 2-6
Priority encoder, 5-4
Processor status word‚ See PSW
Product information, ordering, 1-6
PROG#, 16-11, 16-12, B-15
Program counter‚ See PC
Programming modes, 16-1–16-45
algorithms, 16-21, 16-22, 16-24, 16-29
auto, 16-2
entering, 16-14, 16-15
exiting, 16-15
hardware requirements, 16-14
pin functions, 16-11–16-13
selecting, 16-14
serial port, 16-2
slave, 16-2
Programming voltages, 13-1, 14-2, 16-13, B-18
calculating, 16-16
Program-word routine, 16-23
PSW, 2-4, 3-11, 5-13
flags, and instructions, A-5
PTS, 2-4, 2-6, 2-11, 5-1
A/D scan mode, 5-26–5-31
and A/D converter, 5-26, 5-27
and EPA, 5-31–5-41
and SSIO handshaking, 8-6
and SSIO port, 8-5, 8-6
block transfer mode, 5-24
cycle execution time, 5-10
cycle, defined, 5-24
interrupt latency, 5-10
interrupt processing flow, 5-2
PWM modes, 5-31–5-41
PWM remap mode, 5-37
PWM toggle mode, 5-32, 10-15, 10-16
single transfer mode, 5-21
vectors, memory locations, 4-3, 4-4
See also PWM
Index-9
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