Intel 8XC196K Series User Manual page 511

8XC196K x , J x , CA USER'S MANUAL
Name Type
††
BHE# O
†
BREQ# O
†
BUSWIDTH I
CLKOUT O
COMP1:0 O
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
B-10
Table B-6. Signal Descriptions (Continued)
Byte High Enable
The chip configuration register 0 (CCR0) determines whether this pin functions
as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0 selects WRH#.
During 16-bit bus cycles, this active-low output signal is asserted for word reads
and writes and high-byte reads and writes to external memory. BHE# indicates
that valid data is being transferred over the upper half of the system data bus.
Use BHE#, in conjunction with AD0, to determine which memory byte is being
transferred over the system bus:
BHE# AD0 Byte(s) Accessed
0 0 both bytes
0 1 high byte only
1 0 low byte only
BHE# is multiplexed with P5.5 and WRH#.
Bus Request
This active-low output signal is asserted during a hold cycle when the bus
controller has a pending external memory cycle.
The device can assert BREQ# at the same time as or after it asserts HLDA#.
Once it is asserted, BREQ# remains asserted until HOLD# is removed.
You must enable the bus-hold protocol before using this signal (see "Enabling
the Bus-hold Protocol (8XC196Kx Only)" on page 15-18).
BREQ# is multiplexed with P2.3.
Bus Width
The chip configuration register bits, CCR0.1 and CCR1.2, along with the
BUSWIDTH pin, control the data bus width. When both CCR bits are set, the
BUSWIDTH signal selects the external data bus width. When only one CCR bit
is set, the bus width is fixed at either 16 or 8 bits, and the BUSWIDTH signal
has no effect.
CCR0.1 CCR1.2 BUSWIDTH
0 1 N/A
1 0 N/A
1 1 high
1 1 low
BUSWIDTH is multiplexed with P5.7.
Clock Output
Output of the internal clock generator. The CLKOUT frequency is ½ the
oscillator input frequency (XTAL1). CLKOUT has a 50% duty cycle.
CLKOUT is multiplexed with P2.7 and PACT#.
Event Processor Array (EPA) Compare Pins
These signals are the output of the EPA compare-only channels. These pins
are multiplexed with other signals and may be configured as standard I/O.
COMP1:0 are multiplexed as follows: COMP0/P6.0/EPA8 and
COMP1/P6.1/EPA9.
Description
fixed 8-bit data bus
fixed 16-bit data bus
16-bit data bus
8-bit data bus