Intel 8XC196K Series User Manual page 352

Table 15-1. External Memory Interface Signals (Continued)
Function
Type
Name
CLKOUT O Clock Output
Output of the internal clock generator. The CLKOUT frequency is ½
the oscillator frequency input (XTAL1). CLKOUT has a 50% duty
cycle.
EA# I External Access
EA# is sampled and latched only on the rising edge of RESET#.
Changing the level of EA# after reset has no effect. Accesses to
special-purpose and program memory partitions are directed to
internal memory if EA# is held high and to external memory if EA# is
held low. (See Table 4-1 on page 4-2 for address ranges of special-
purpose and program memory partitions.)
EA# also controls program mode entry. If EA# is at V
(typically +12.5 V) on the rising edge of RESET#, the device enters
programming mode.
NOTE: When EA# is active, ports 3 and 4 will function only as the
On devices with no internal nonvolatile memory, always connect EA#
to V
†
HLDA# O Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus
as the result of an external device asserting HOLD#.
†
The P2.6 pin does not function as HLDA# on the 87C196CA,
8XC196J x devices.
†
HOLD# I Bus Hold Request
An external device uses this active-low input signal to request control
of the bus. This pin functions as HOLD# only if the pin is configured
for its special function (see "Bidirectional Port Pin Configurations" on
page 6-10) and the bus-hold protocol is enabled. Setting bit 7 of the
window selection register enables the bus-hold protocol.
†
This pin is not implemented on the 87C196CA, 8XC196J x devices.
†
INTOUT# O Interrupt Output
This active-low output indicates that a pending interrupt requires use
of the external bus.
†
This pin is not implemented on the 87C196CA, 8XC196J x devices.
†
INST O Instruction Fetch
This active-high output signal is valid only during external memory
bus cycles. When high, INST indicates that an instruction is being
fetched from external memory. The signal remains high during the
entire bus cycle of an external instruction fetch. INST is low for data
accesses, including interrupt vector fetches and chip configuration
byte reads. INST is low during internal memory fetches.
†
This pin is not implemented on the 87C196CA, 8XC196J x devices.
RD# O Read
Read-signal output to external memory. RD# is asserted only during
external memory reads.
Description
address/data bus. They cannot be used for standard I/O.
.
SS
INTERFACING WITH EXTERNAL MEMORY
voltage
PP
Multiplexed
With
P2.7
—
P2.6
P2.5
AINC#/P2.4
P5.1
P5.3
15-3