Intel 8XC196K Series User Manual page 40

Core
Clock and
Power Mgmt.
I/O SIO SSIO
Note:
The slave port is unique to 8XC196K x devices.
The CAN peripheral is unique to the 8XC196CA.
Figure 2-1. 8XC196K x Block Diagram
CPU
Register File
Register
RAM
CPU SFRs
Figure 2-2. Block Diagram of the Core
Optional
Interrupt
ROM
Controller
Code/Data
PTS
RAM
EPA A/D WDT
RALU
Microcode
Engine
ALU
Master PC
PSW
Registers
ARCHITECTURAL OVERVIEW
Slave
CAN
Port
Memory Controller
Prefetch Queue
Slave PC
Address Register
Data Register
Bus Controller
A2799-02
A2797-01
2-3