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Getting Started
2.5.16
LPC Bus
The LPC bus connects to these devices on the carrier board:
• SMSC LPC47M172 Super I/O*
• Xilinx XC9572XL* POST code display CPLD
®
• Intel
• LPC debug header for LPC testing (X34)
Note:
LPC DMA is not supported by the processor on the Intel
®
Intel
Platform Controller Hub EG20T Development Kit.
2.5.16.1
Super IO (SIO)
The LPC47M172 serves as legacy PS/2* keyboard and mouse controller on the carrier
board. The LPC47M172 Super I/O supports:
• LPC interface
• One UART serial port at the rear I/O panel (see
• Two PS/2 ports located at the rear I/O panel
2.5.16.2
POST Code Display CPLD
I/O writes to port 80h on LPC bus are decoded by the Xilinx XC9572XL* device on the
carrier board and displayed on two 7-segment LEDs.
®
2.5.16.3
Intel
Trusted Platform Module (Intel
The carrier board implements a header (X35) that supports Intel
specification compliant devices.
®
2.5.17
Intel
The Intel
HD Audio jack (X27) is provided on the rear I/O panel. No SPDIF receptacle is
provided on the carrier board. For the front panel, only a 2x5 header (X36) is provided.
2.5.18
Clocks
The COM Express* Module uses a CK-505 clock solution. The BSEL [2:1] signals driven
by the processor are used by the CK-505 to configure the processor external reference
clock.
The carrier board uses several clocks.
the carrier board.
EG20T clock circuit in the carrier board when using the custom CK505 clock generator
on the COM Express module.
January 2012
Document Number: 324213-002
TPM header (X35)
High Definition Audio (Intel
®
HD Audio is enabled through the Realtek ALC888* CODEC. Six port Intel
Figure 9
describes the change required to connect the Intel
®
Intel
Atom™ Processor E660 with Intel
®
Atom™ Processor E660 with
Section
2.4.10)
®
TPM ) Header
®
HD Audio )
Figure 8
describes the clock circuit connections in
®
Platform Controller Hub EG20T Development Kit
®
TPM 1.2
®
®
PCH
User Manual
27
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