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8XC196K x , J x , CA USER'S MANUAL
Because port 0 is permanently configured as an input-only port, it has no configuration registers.
Its single register, P0_PIN, can be read to determine the current state of the pin. The register is
byte-addressable and can be windowed. (See Chapter 4, "Memory Partitions.")
Table 6-2 lists the standard input-only port pins and Table 6-3 describes the P0_PIN status regis-
ter.
Port Pin
P0.7:0 (Kx),
P0.7:2 (CA, Jx)
Mnemonic
P0_PIN
1FDAH
6.2.1
Standard Input-only Port Operation
Figure 6-1 is a schematic of an input-only port pin. Transistors Q1 and Q2 serve as electrostatic
discharge (ESD) protection devices; they are referenced to V
an additional ESD protection device; it is referenced to V
current flow through Q3 to acceptable levels. At this point, the input signal is sent to the analog
multiplexer and to the digital level-translation buffer. The level-translation buffer converts the in-
put signals to work with the V
is Schmitt-triggered for improved noise immunity. The signals are latched in the P0_PIN register
and are output onto the internal bus when P0_PIN is read.
6-2
Table 6-2. Standard Input-only Port Pins
Special-function
Signal(s)
ACH7:0 (Kx),
ACH7:2 (CA, Jx)
Table 6-3. Input-only Port Registers
Address
Port 0 Input
Each bit of P0_PIN reflects the current state of the corresponding
port 0 pin.
and V
digital voltage levels used by the CPU core. This buffer
CC
SS
Special-function
Signal Type
Input
Description
and ANGND. Transistor Q3 is
REF
(digital ground). Resistor R1 limits
SS
Associated
Peripheral
A/D converter
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