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8XC196K x , J x , CA USER'S MANUAL
13.5.2 Issuing the Reset (RST) Instruction
The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times.
It also clears the processor status word (PSW), sets the master program counter (PC) to 2080H,
and resets the special function registers (SFRs). See Table C-2 on page C-2 for the reset values
of the SFRs.
Putting pull-ups on the address/data bus causes unimplemented areas of memory to be read as
FFH. If unused internal OTPROM memory is set to FFH, then execution from any unused mem-
ory locations will reset the device.
13.5.3 Issuing an Illegal IDLPD Key Operand
The device resets itself if an illegal key operand is used with the idle/powerdown (IDLPD) com-
mand. The legal keys are "1" for idle mode and "2" for powerdown mode. If any other value is
used, the device executes a reset sequence. (See Appendix A for a description of the IDLPD com-
mand.)
13.5.4 Enabling the Watchdog Timer
The watchdog timer (WDT) is a 16-bit counter that resets the device when the counter overflows
(every 64K state times). The WDE bit (bit 3) of CCR1 controls whether the watchdog is enabled
immediately or is disabled until the first time it is cleared. Clearing WDE activates the watchdog.
Setting WDE makes the watchdog timer inactive, but you can activate it by clearing the watchdog
register. Once the watchdog is activated, only a reset can disable it.
You must write two consecutive bytes to the watchdog register (location 0AH) to clear it. The
first byte must be 1EH and the second must be E1H. We recommend that you disable interrupts
before writing to the watchdog register. If an interrupt occurs between the two writes, the watch-
dog register will not be cleared.
If enabled, the watchdog continues to run in idle mode. The device must be awakened within 64K
state times to clear the watchdog; otherwise, the watchdog will reset the device, which causes it
to exit idle mode.
13.5.5 Detecting Oscillator Failure
The ability to sense an oscillator failure is important in safety-sensitive applications. This device
provides a feature that can detect a failed oscillator and reset itself. Low-frequency oscillation,
typically 100 KHz or below, is sensed as a failure. If enabled, the oscillator fail detect (OFD) cir-
cuitry resets the device in the event of an oscillator failure. This feature is enabled by program-
ming the OFD bit (bit 0) in the USFR. (See "Enabling the Oscillator Failure Detection Circuitry"
on page 16-8 for details.)
13-12
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