Intel 8XC196K Series User Manual page 629

8XC196K x , J x , CA USER'S MANUAL
PTS routine
PTS transfer
PTS vector
PWM
quantizing error
RALU
repeatability error
reserved memory
resolution
sample capacitor
Glossary-8
The entire microcoded response to multiple PTS
interrupt requests. The PTS routine is controlled by
the contents of the PTS control block.
The movement of a single byte or word from the
source memory location to the destination memory
location.
A location in special-purpose memory that holds the
starting address of a PTS control block.
Pulse-width modulated (outputs). The EPA can be
used with or without the PTS to generate PWM
outputs.
An unavoidable A/D conversion error that results
simply from the conversion of a continuous voltage to
its integer digital representation. Quantizing error is
always ± 0.5 LSB and is the only error present in an
ideal A/D converter.
Register arithmetic-logic unit. A part of the CPU that
consists of the ALU, the PSW, the master PC, the
microcode engine, a loop counter, and six registers.
The difference between
transitions from different actual characteristics taken
from the same converter on the same channel with the
same temperature, voltage, and frequency conditions.
The amount of repeatability error depends on the
comparator's ability to resolve very similar voltages
and the extent to which random noise contributes to
the error.
A memory location that is reserved for factory use or
for future expansion. Do not use a reserved memory
location except to initialize it with FFH.
The number of input voltage levels that an A/D
converter can unambiguously distinguish between.
The number of useful bits of information that the
converter can return.
A small (2–3 pF) capacitor used in the A/D converter
circuitry to store the input voltage on the selected
input channel.
corresponding code