Code Execution; Instruction Format - Intel 8XC196K Series User Manual

The RALU uses the upper- and lower-word registers together for the 32-bit instructions and as
temporary registers for many instructions. These registers have their own shift logic and are used
for operations that require logical shifts, including normalize, multiply, and divide operations.
The six-bit loop counter counts repetitive shifts. The second-operand register stores the second
operand for two-operand instructions, including the multiplier during multiply operations and the
divisor during divide operations. During subtraction operations, the output of this register is com-
plemented before it is moved into the ALU.
The RALU speeds up calculations by storing constants (e.g., 0, 1, and 2) in the constants register
so that they are readily available when complementing, incrementing, or decrementing bytes or
words. In addition, the constants register generates single-bit masks, based on the bit-select reg-
ister, for bit-test instructions.
2.3.3.1

Code Execution

The RALU performs most calculations for the device, but it does not use an accumulator. Instead
it operates directly on the lower register file, which essentially provides 256 accumulators. Be-
cause data does not flow through a single accumulator, the device's code executes faster and more
efficiently.
2.3.3.2

Instruction Format

MCS 96 microcontrollers combine a large set of general-purpose registers with a three-operand
instruction format. This format allows a single instruction to specify two source registers and a
separate destination register. For example, the following instruction multiplies two 16-bit vari-
ables and stores the 32-bit result in a third variable.
MUL RESULT, FACTOR_1, FACTOR_2
An 80C186 device requires four instructions to accomplish the same operation. The following ex-
ample shows the equivalent code for an 80C186 device.
MOV AX, FACTOR_1
MUL FACTOR_2
MOV RESULT, AX
MOV RESULT+2, DX
ARCHITECTURAL OVERVIEW
;multiply FACTOR_1 and FACTOR_2
;and store answer in RESULT
;(RESULT)←(FACTOR_1 × FACTOR_2)
;move FACTOR_1 into accumulator (AX)
;(AX)←FACTOR1
;multiply FACTOR_2 and AX
;(DX:AX)←(AX)×(FACTOR_2)
;move lower byte into RESULT
;(RESULT)←(AX)
;move upper byte into RESULT+2
;(RESULT+2)←(DX)
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