Intel 8XC196K Series User Manual page 592

SLP_CON
(8XC196K x )
The slave port control (SLP_CON) register is used to configure the slave port. Only the slave can
access the register.
7
KQ, KR —
7
KS, KT —
Bit Bit
Number Mnemonic
7:5 — Reserved; always write as zeros.
†
4 SME Shared Memory Enable
Enables slave port shared memory mode.
1 = shared memory mode
0 = standard slave mode
3 SLP Slave Port Enable
This bit enables or disables the slave port.
1 = enables the slave port
0 = disables the slave port and clears the command buffer empty (CBE),
2 SLPL
Slave Port Latch
In standard slave mode only, this bit determines the source of the internal
control signal, SLP_ADDR. When SLP_ADDR is held high, the master can
write to the SLP_CMD register and read from the SLP_STAT register. When
SLP_ADDR is held low, the master can write to the P3_PIN register and read
from the P3_REG register.
1 = SLP1 (P3.1) via master's AD1 signal. Use with multiplexed bus.
0 = SLPALE (P5.0) via master's A1 signal. Use with demultiplexed bus.
In shared memory mode, this bit has no function.
1 IBEMSK Input Buffer Empty Mask
Controls whether the IBE flag (in SLP_STAT) asserts the SLPINT signal.
In shared memory mode, this bit has no effect on the SLPINT signal.
0 OBFMSK Output Buffer Full Mask
Controls whether the OBF flag (in SLP_STAT) asserts the SLPINT signal.
In shared memory mode, this bit has no effect on the SLPINT signal.
†
On the 8XC196KQ, KR devices this bit is reserved; always write as zero.
— — —
— — SME
input buffer empty (IBE), and output buffer full (OBF) flags in the
SLP_STAT register.
Address:
Reset State:
SLP SLPL IBEMSK
SLP SLPL IBEMSK
Function
REGISTERS
SLP_CON
1FFBH
00H
0
OBFMSK
0
OBFMSK
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