Intel 8XC196K Series User Manual page 152

P2.6/HLDA#
P2.7/CLKOUT
P2.7
Port 5
P5.0/ALE
P5.1/INST
P5.2/WR#/WRL#
The HLDA# pin is used in systems with more than one processor
using the system bus. This device asserts HLDA# to indicate that it
has freed the bus in response to HOLD# and another processor can
take control. (This signal is active low to avoid misinterpretation by
external hardware immediately after reset.)
P2.6/HLDA# is the enable pin for ONCE mode in certain 8XC196Kx
devices (see Chapter 14, "Special Operating Modes") and one of the
enable pins for Intel-reserved test modes. Because a low input during
reset could cause the device to enter ONCE mode or a reserved test
mode, exercise caution if you use this pin for input. Be certain that
your system meets the V
during reset to prevent inadvertent entry into ONCE mode or a test
mode.
8XC196CA, JQ, JR, JT, JV, KQ, KR: Following reset, P2.7 carries
the strongly driven CLKOUT signal. It is not held high. When P2.7
is configured as CLKOUT, it is always a complementary output.
8XC196KS, KT: Following reset, P2.7 is weakly held high.
A value written to the upper bit of P2_REG (bit 7) is held in a buffer
until the corresponding P2_MODE bit is cleared, at which time the
value is loaded into the P2_REG bit. A value read from P2_REG.7 is
the value currently in the register, not the value in the buffer.
Therefore, any change to P2_REG.7 can be read only after
P2_MODE.7 is cleared.
After reset, the device configures port 5 to match the external system.
The following paragraphs describe the states of the port 5 pins after
reset and until your software writes to the P5_MODE register.
Writing to P5_MODE not only configures the pins but also turns off
the transistor that weakly holds the pins high (Q4 in Figure 6-2 on
page 6-8). For this reason, even if port 5 is to be used as it is
configured at reset, you should still write data into P5_MODE.
If EA# is high on reset (internal access), the pin is weakly held high
until your software writes to P5_MODE. If EA# is low on reset
(external access), either ALE or ADV# is activated as a system
control pin, depending on the ALE bit of CCR0. In either case, the
pin becomes a true complementary output.
8XC196Kx Only: This pin remains weakly held high until your
software writes configuration data into P5_MODE.
This pin remains weakly held high until your software writes config-
uration data into P5_MODE.
specification (listed in the datasheet)
IH
I/O PORTS
6-13