Intel 8XC196K Series User Manual page 192

SSIO x _CON
x = 0–1
The synchronous serial control x (SSIO x _CON) registers control the communications mode and
handshaking. The two least-significant bits indicate whether an overflow or underflow has occurred
and whether the channel is ready to transmit or receive.
7
M/S# T/R#
Bit Bit
Number Mnemonic
†
7 M/S#
†
6 T/R#
5 TRT
4 THS
3 STE
†
The M/S# and T/R# bits specify four possible configurations: master transmitter, master receiver,
slave transmitter, or slave receiver.
Figure 8-6. Synchronous Serial Control x (SSIO x _CON) Registers
TRT THS
Master/Slave Select
Configures the channel as either master or slave.
0 = slave; SC x is an external clock input to SSIO x _BUF
1 = master; SC x is an output driven by the SSIO baud-rate generator
Transmit/Receive Select
Configures the channel as either transmitter or receiver.
0 = receiver; SD x is an input to SSIO x _BUF
1 = transmitter; SD x is an output driven by the output of SSIO x _BUF
Transmitter/Receiver Toggle
Controls whether receiver and transmitter switch roles at the end of each
transfer.
0 = do not switch
1 = switch; toggle T/R# and clear TRT at the end of the current transfer
Setting TRT allows the channel configuration to change immediately on
transfer completions, thus avoiding possible contention on the data line.
Transceiver Handshake Select
Enables and disables handshaking. The THS, STE, and ATR bits must
be set for handshaking modes.
0 = disables handshaking
1 = enables handshaking
Single Transfer Enable
Enables and disables transfer of a single byte. Unless ATR is set, STE is
automatically cleared at the end of a transfer. The THS, STE, and ATR
bits must be set for handshaking modes.
0 = disable transfers
1 = allow transmission or reception of a single byte
SYNCHRONOUS SERIAL I/O (SSIO) PORT
Address:
Reset State:
STE ATR
Function
1FB1H, 1FB3H
00H
0
OUF TBS
8-11