Intel 8XC196K Series User Manual page 519

8XC196K x , J x , CA USER'S MANUAL
Name Type
†
T1DIR I
T2DIR I
TXCAN O
(CA only)
TXD O
V PWR
CC
V PWR
PP
V PWR
REF
V GND
SS
WR# O
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
B-18
Table B-6. Signal Descriptions (Continued)
Timer 1 External Direction
External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high
and decrements when it is low. Also used in conjunction with T1CLK for
quadrature counting mode.
T1DIR is multiplexed with P6.3.
Timer 2 External Direction
External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high
and decrements when it is low. Also used in conjunction with T2CLK for
quadrature counting mode.
T2DIR is multiplexed with P1.2 and EPA2.
Transmit
This signal carries messages from the integrated CAN controller to other nodes
on the CAN bus.
Transmit Serial Data
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode
0, it is the serial clock output.
TXD is multiplexed with P2.0 and PVER.
Digital Supply Voltage
Connect each V pin to the digital supply voltage.
CC
Programming Voltage
During programming, the V
Exceeding the maximum V
V also causes the device to exit powerdown mode when it is driven low for at
PP
least 50 ns. Use this method to exit powerdown only when using an external
clock source because it enables the internal phase clocks, but not the internal
oscillator. See "Driving the Vpp Pin Low" on page 14-5.
On devices with no internal nonvolatile memory, connect V
Reference Voltage for the A/D Converter
This pin also supplies operating voltage to both the analog portion of the A/D
converter and the logic used to read Port 0.
Digital Circuit Ground
Connect each V pin to ground through the lowest possible impedance path.
SS
Write
The chip configuration register 0 (CCR0) determines whether this pin functions
as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0 selects WRL#.
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
WR# is multiplexed with P5.2, SLPWR#, and WRL#.
Description
pin is typically at +12.5 V (V
PP
voltage specification can damage the device.
PP
voltage).
PP
to V .
PP CC