Intel 8XC196K Series User Manual page 575

Table of Contents

8XC196K x, J x , CA USER'S MANUAL

When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending

(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.

Software can generate an interrupt by setting the corresponding interrupt pending bit.

When set, this bit indicates that the corresponding interrupt is pending. The interrupt bit is

cleared when processing transfers to the corresponding interrupt vector.

The standard interrupt vector locations are as follows:

Bit Mnemonic Interrupt

EPA 4–9 capture/compare channel events, EPA 0–1 compare channel events, EPA 0–

9 capture/compare overruns, and timer overflows can generate this multiplexed interrupt.

The EPA mask and pending registers decode the EPA x interrupt. Write the EPA mask

registers to enable the interrupt sources; read the EPA pending registers (EPA_PEND

and EPA_PEND1) to determine which source caused the interrupt.

Bits 6–7 are reserved on the 87C196CA, 8XC196J x devices. For compatibility with future devices,

write zeros to these bits.

Slave Port Input Buffer Full

Slave Port Output Buffer Empty

A/D Conversion Complete

EPA Capture/Compare Channel 0

EPA Capture/Compare Channel 1

EPA Capture/Compare Channel 2

EPA Capture/Compare Channel 3

Multiplexed EPA

Reset State:

Standard Vector