Page 3 8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQ Embedded Microcontroller User’s Manual May 1996...
Page 4 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including in- fringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Page 5: Table Of Contents
ADDRESS SPACES ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS........3-1 3.1.1 Compatibility with the MCS® 51 Architecture ............3-2 8XC251SA, SB, SP, SQ MEMORY SPACE ..............3-5 3.2.1 On-chip General-purpose Data RAM ................3-8 3.2.2 On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ) .....3-8 3.2.2.1...
Page 6 8XC251SA, SB, SP, SQ USER’S MANUAL 3.3.2.3 Extended Stack Pointer, SPX ................3-15 SPECIAL FUNCTION REGISTERS (SFRS) ............... 3-16 CHAPTER 4 DEVICE CONFIGURATION CONFIGURATION OVERVIEW ..................4-1 DEVICE CONFIGURATION ..................4-1 THE CONFIGURATION BITS..................4-4 CONFIGURATION BYTE LOCATION SELECTOR (UCON)......... 4-5 CONFIGURING THE EXTERNAL MEMORY INTERFACE...........
Page 7 5.5.4 Calls and Returns ....................5-15 PROGRAM STATUS WORDS ..................5-16 CHAPTER 6 INTERRUPT SYSTEM OVERVIEW ........................6-1 8XC251SA, SB, SP, SQ INTERRUPT SOURCES ............6-3 6.2.1 External Interrupts .....................6-3 6.2.2 Timer Interrupts ......................6-4 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT........6-5 SERIAL PORT INTERRUPT..................6-5 INTERRUPT ENABLE ....................
Page 8 8XC251SA, SB, SP, SQ USER’S MANUAL TIMER/COUNTER OPERATION................... 8-1 TIMER 0......................... 8-3 8.3.1 Mode 0 (13-bit Timer) ....................8-4 8.3.2 Mode 1 (16-bit Timer) ....................8-4 8.3.3 Mode 2 (8-bit Timer With Auto-reload) ..............8-5 8.3.4 Mode 3 (Two 8-bit Timers) ..................8-5 TIMER 1......................... 8-5 8.4.1...
Page 9 CONTENTS 10.2 MODES OF OPERATION.................... 10-4 10.2.1 Synchronous Mode (Mode 0) ..................10-4 10.2.1.1 Transmission (Mode 0) ..................10-4 10.2.1.2 Reception (Mode 0) ....................10-5 10.2.2 Asynchronous Modes (Modes 1, 2, and 3) .............10-6 10.2.2.1 Transmission (Modes 1, 2, 3) ................10-6 10.2.2.2 Reception (Modes 1, 2, 3) ..................10-6 10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3)........
Page 10 8XC251SA, SB, SP, SQ USER’S MANUAL 12.2.2 Power Off Flag ......................12-1 12.3 IDLE MODE ......................... 12-4 12.3.1 Entering Idle Mode ....................12-4 12.3.2 Exiting Idle Mode ....................12-5 12.4 POWERDOWN MODE ....................12-5 12.4.1 Entering Powerdown Mode ..................12-6 12.4.2 Exiting Powerdown Mode ..................12-6 12.5...
Page 11 CONTENTS CHAPTER 14 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14.1 GENERAL........................14-1 14.1.1 Programming Considerations for On-chip Code Memory ........14-2 14.1.2 EPROM Devices .....................14-3 14.2 PROGRAMMING AND VERIFYING MODES.............. 14-3 14.3 GENERAL SETUP....................... 14-3 14.4 PROGRAMMING ALGORITHM................... 14-5 14.5 VERIFY ALGORITHM....................14-6 14.6 PROGRAMMABLE FUNCTIONS ................
Page 12 Address Spaces for the MCS® 51 Architecture ............3-3 Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture.....3-4 8XC251SA, SB, SP, SQ Address Space ..............3-6 Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space ....3-7 The Register File ......................3-11 Register File Locations 0–7..................3-12 Dedicated Registers in the Register File and their Corresponding SFRs....3-14...
Page 13 CONTENTS FIGURES Figure Page 8-12 T2CON: Timer 2 Control Register ................8-17 Programmable Counter Array..................9-3 PCA 16-bit Capture Mode ....................9-6 PCA Software Timer and High-speed Output Modes...........9-8 PCA Watchdog Timer Mode..................9-10 PCA 8-bit PWM Mode ....................9-11 PWM Variable Duty Cycle ..................9-12 CMOD: PCA Timer/Counter Mode Register...............9-13 CCON: PCA Timer/Counter Control Register.............9-14 CCAPMx: PCA Compare/Capture Module Mode Registers........9-15...
Page 14 Bus Diagram for Example 7: 80C251SB in Page Mode ...........13-30 14-1 Setup for Programming and Verifying Nonvolatile Memory........14-5 14-2 Program/Verify Bus Cycles..................14-6 8XC251SA, SB, SP, SQ 44-pin PLCC Package ............B-1 8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages ......B-3...
Page 15 Minimum Times to Fetch Two Bytes of Code...............3-9 Register Bank Selection .....................3-12 Dedicated Registers in the Register File and their Corresponding SFRs....3-15 8XC251SA, SB, SP, SQ SFR Map and Reset Values ..........3-17 Core SFRs........................3-18 I/O Port SFRs ......................3-18 Serial I/O SFRs ......................3-19 Timer/Counter and Watchdog Timer SFRs ..............3-19...
Page 16 Summary of Control Instructions ................A-24 A-28 Flag Symbols......................A-26 PLCC/DIP Pin Assignments Listed by Functional Category........B-2 Signal Descriptions...................... B-3 Memory Signal Selections (RD1:0) ................B-7 8XC251SA, SB, SP, SQ SFR Map................C-2 Core SFRs........................C-3 I/O Port SFRs ......................C-3...
Page 17 CONTENTS TABLES Table Page Serial I/O SFRs ......................C-4 Timer/Counter and Watchdog Timer SFRs ..............C-4 Programmable Counter Array (PCA) SFRs..............C-5 Register File ........................ C-6...
Page 19: Guide To This Manual
Guide to This Manual...
Page 21: Manual Contents
PCA interrupt, and a serial port interrupt. This chapter also discusses the interrupt priority scheme, interrupt enable, interrupt processing, and interrupt response time. † The 8XC251SA, SB, SP, SQ products are also collectively referred to as 8XC251S x .
Page 22 8XC251SA, SB, SP, SQ USER’S MANUAL Chapter 7, “Input/Output Ports” — describes the four 8-bit I/O ports (ports 0–3) and discusses their configuration for general-purpose I/O, external memory accesses (ports 0, 2), and alterna- tive special functions. Chapter 8, “Timer/Counters and WatchDog Timer” — describes the three on-chip tim- er/counters and discusses their application.
Page 23: Notational Conventions And Terminology
GUIDE TO THIS MANUAL Appendix B, “Signal Descriptions” — describes the function(s) of each device pin. Descrip- tions are listed alphabetically by signal name. This appendix also provides a list of the signals grouped by functional category. Appendix C, “Registers” — accumulates, for convenient reference, copies of the register defi- nition figures that appear throughout the manual.
Page 24 8XC251SA, SB, SP, SQ USER’S MANUAL Instructions Instruction mnemonics are shown in upper case to avoid confusion. When writing code, either upper case or lower case may be used. Logic 0 (Low) An input voltage level equal to or less than the maximum value of...
Page 25: Related Documents
RELATED DOCUMENTS The following documents contain additional information that is useful in designing systems that incorporate the 8XC251Sx microcontroller. To order documents, please call Intel Literature Ful- fillment (1-800-548-4725 in the U.S. and Canada; +44(0) 793-431155 in Europe). Embedded Microcontrollers...
Page 26: Data Sheet
8XC251SA, SB, SP, SQ USER’S MANUAL 1.3.1 Data Sheet The data sheet is included in Embedded Microcontrollers and is also available individually. 8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller Order Number 272783 (Commercial/Express) 1.3.2 Application Notes The following application notes apply to the MCS 251 microcontroller.
Page 27: Application Support Services
Intel maintains several CompuServe forums that provide a means for you to gather information, share discoveries, and debate issues. Type “go intel” for access. The INTELC forum is set up to support designers using various Intel components. For information about CompuServe access and...
Page 28: Faxback Service
1.4.4 Bulletin Board System (BBS) Intel’s Brand Products and Applications Support bulletin board system (BBS) lets you download files to your PC. The BBS has the latest ApBUILDER software, hypertext manuals and datasheets, software drivers, firmware upgrades, application notes and utilities, and quality and...
Page 29 GUIDE TO THIS MANUAL Any customer with a PC and modem can access the BBS. The system provides automatic config- uration support for 1200- through 19200-baud modems. Use these modem settings: no parity, 8 data bits, and 1 stop bit (N, 8, 1). To access the BBS, just dial the telephone number (see Table 1-1 on page 1-7) and respond to the system prompts.
Page 31: Architectural Overview
Architectural Overview...
Page 33 It is also well suited for communications applications, such as phone terminals, business/feature phones, and phone switching and transmission systems. This manual covers all memory options of the 8XC251SA, SB, SP, SQ and these options are listed in Table 2-1.
Page 34 Instruction Sequencer Handler SRC1 (8) SRC2 (8) Serial I/O Clock & Reset Data Register Memory File Peripherals Interface DST (16) ® 251 Microcontroller Core Clock & Reset 8XC251SA/SB/SP/SQ Microcontroller A4214-01 Figure 2-1. Functional Block Diagram of the 8XC251SA, SB, SP, SQ...
Page 35: 8Xc251Sa, Sb, Sp, Sq Architecture
ARCHITECTURAL OVERVIEW 8XC251SA, SB, SP, SQ ARCHITECTURE Figure 2-1 is a functional block diagram of the 8XC251SA, SB, SP, SQ. The core, which is com- mon to all MCS 251 microcontrollers, is described in section 2.2, “MCS 251 Microcontroller Core.” Each microcontroller type in the family has its own on-chip peripherals, I/O ports, external system bus, size of on-chip RAM, and type and size of on-chip program memory.
Page 36: Mcs 251 Microcontroller Core
8XC251SA, SB, SP, SQ USER’S MANUAL The 8XC251Sx has two power-saving modes. In idle mode, the CPU clock is stopped, while clocks to the peripherals continue to run. In powerdown mode, the on-chip oscillator is stopped, and the chip enters a static state. An enabled interrupt or a hardware reset can bring the chip back to its normal operating mode from idle or powerdown.
Page 37: Cpu
ARCHITECTURAL OVERVIEW 2.2.1 Figure 2-2 is a functional block diagram of the CPU (central processor unit). The 8XC251Sx fetches instructions from on-chip code memory two bytes at a time, or from external memory in single bytes. The instructions are sent over the 16-bit code bus to the execution unit. You can con- figure the 8XC251Sx to operate in page mode for accelerated instruction fetches from external memory.
Page 38: Clock And Reset Unit
8XC251SA, SB, SP, SQ USER’S MANUAL 2.2.2 Clock and Reset Unit The timing source for the 8XC251Sx can be an external oscillator or an internal oscillator with an external crystal/resonator (see Chapter 11, “Minimum Hardware Setup”). The basic unit of time in MCS 251 microcontrollers is the state time (or state), which is two oscillator periods (see Figure 2-3).
Page 39: Interrupt Handler
2.2.5 On-chip RAM The 8XC251SA and 8XC251SB have 1-Kbyte of on-chip data RAM at locations 20H–41FH. The 8XC251SP and 8XC251SQ have 512 bytes of on-chip data RAM at locations 20H–21FH. These RAM locations can be accessed with direct, indirect, and displacement addressing. Ninety-six of these locations (20H–7FH) are bit addressable.
Page 40: Programmable Counter Array (Pca)
8XC251SA, SB, SP, SQ USER’S MANUAL The watchdog timer is a circuit that automatically resets the 8XC251Sx in the event of a hardware or software upset. When enabled by software, the watchdog timer begins running, and unless software intervenes, the timer reaches a maximum count and initiates a chip reset. In normal op- eration, software periodically clears the timer register to prevent the reset.
Page 41: Address Spaces
Address Spaces...
Page 43 CHAPTER 3 ADDRESS SPACES ® 251 microcontrollers have three address spaces: a memory space, a special function reg- ister (SFR) space, and a register file. This chapter describes these address spaces as they apply to all MCS 251 microcontrollers and to the 8XC251Sx in particular. It also discusses the compati- ®...
Page 44: Compatibility With The Mcs® 51 Architecture
8 registers. The 32 bytes required for these banks occupy locations 00:0000H– 00:001FH in the memory space. Register file locations 8–63 do not appear in the memory space. See “8XC251SA, SB, SP, SQ Register File” on page 3-10 for a further description of the register file.
Page 45 ADDRESS SPACES The register file (registers R0–R7) comprises four switchable register banks, each having eight registers. The 32 bytes required for the four banks occupy locations 00H–1FH in the on-chip data memory. Figure 3-3 shows how the address spaces in the MCS 51 architecture map into the address spaces in the MCS 251 architecture;...
Page 46 8XC251SA, SB, SP, SQ USER’S MANUAL Memory Address Space 16 Mbytes FFFFH SFR Space MCS ® 51 Architecture 512 Bytes Code Memory S:1FFH 0000H FF:0000H S:100H MCS 51 Architecture SFRs S:07FH 02:0000H S:000H FFFFH MCS 51 Architecture External Data Memory...
Page 47: 8Xc251Sa, Sb, Sp, Sq Memory Space
128 bytes are accessible by indirect addressing only. In the MCS 251 architecture, all locations in region 00: are accessible by direct, indirect, and displacement addressing (see “8XC251SA, SB, SP, SQ Memory Space” on page 3-5). The 128-byte SFR space for MCS 51 microcontrollers is mapped into the 512-byte SFR space of the MCS 251 architecture starting at address S:080H, as shown in Figure 3-3.
Page 48 FE:0000H Indirect and Displacement Addressing Regions 02–FD (16 Mbytes) are Reserved 01:FFFFH 01:0000H Direct Addressing 00:FFFFH (64 Kbytes) 00:0080H Bit Addressing 00:007FH 00:0020H (96 Bytes) Register Addressing 00:001FH 00:0000H (32 Bytes) A4385-01 Figure 3-4. 8XC251SA, SB, SP, SQ Address Space...
Page 49 On-chip RAM 512 or 1024 Bytes Registers R0-R7 †† 00:0000H † Eight-byte configuration array (FF:FFF8H - FF:FFFFH) †† Four banks of registers R0-R7 (32 bytes, 00:0000H - 00:001FH) A4382-02 Figure 3-5. Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space...
Page 50: On-Chip General-Purpose Data Ram
Figure 3-5 on page 3-7 shows how areas of the memory space are implemented by on-chip RAM, on-chip ROM/OTPROM/EPROM, and external memory. The first 32 bytes of on-chip RAM store banks 0–3 of the register file (see “8XC251SA, SB, SP, SQ Register File” on page 3-10). 3.2.1 On-chip General-purpose Data RAM On-chip RAM (512 bytes or 1 Kbyte) is provided for general data storage (Figure 3-5).
Page 51: Accessing On-Chip Code Memory In Region 00
ADDRESS SPACES Table 3-2. Minimum Times to Fetch Two Bytes of Code Type of Code Memory State Times On-chip Code Memory External Memory (page mode) External Memory (nonpage mode) NOTE If your program executes exclusively from on-chip ROM/OTPROM/EPROM (not from external memory), beware of executing code from the upper eight bytes of the on-chip ROM/OTPROM/EPROM (FF:1FF8H–FF:1FFFH for 8 Kbytes, FF:3FF8H–FF:3FFFH for 16 Kbytes).
Page 52: External Memory
8XC251SA, SB, SP, SQ USER’S MANUAL 3.2.3 External Memory Regions 01:, FE:, and portions of regions 00: and FF: of the memory space are implemented as external memory (Figure 3-5 on page 3-7). For discussions of external memory see “Configuring the External Memory Interface”...
Page 53 ADDRESS SPACES Byte Registers Note: R10 = B R11 = ACC Register File Word Registers Locations 32-55 are Reserved WR24 WR26 WR28 WR30 WR16 WR18 WR20 WR22 WR10 WR12 WR14 Dword Registers DR56 = DPX DR60 = SPX Banks 0-3 DR24 DR28 DR16...
Page 54 8XC251SA, SB, SP, SQ USER’S MANUAL Register file locations 0–7 actually consist of four switchable banks of eight registers each, as il- lustrated in Figure 3-7. The four banks are implemented as the first 32 bytes of on-chip RAM and are always accessible as locations 00:0000H–00:001FH in the memory address space.†...
Page 55: Byte, Word, And Dword Registers
ADDRESS SPACES 3.3.1 Byte, Word, and Dword Registers Depending on its location in the register file, a register is addressable as a byte, a word, and/or a dword, as shown on the right side of Figure 3-6. A register is named for its lowest numbered byte location.
Page 56 8XC251SA, SB, SP, SQ USER’S MANUAL Instructions in the MCS 51 architecture use the accumulator as the primary register for data moves and calculations. However, in the MCS 251 architecture, any of registers R1–R15 can serve for these tasks†. As a result, the accumulator does not play the central role that it has in MCS 51 microcontrollers.
Page 57: Extended Data Pointer, Dpx
ADDRESS SPACES 3.3.2.2 Extended Data Pointer, DPX Dword register DR56 is the extended data pointer, DPX (Figure 3-8). The lower three bytes of DPX (DPL, DPH, and DPXL) are accessible as SFRs. DPL and DPH comprise the 16-bit data pointer DPTR. While instructions in the MCS 51 architecture always use DPTR as the data point- er, instructions in the MCS 251 architecture can use any word or dword register as a data pointer.
Page 58: Special Function Registers (Sfrs)
8XC251SA, SB, SP, SQ USER’S MANUAL SPECIAL FUNCTION REGISTERS (SFRS) The special function registers (SFRs) reside in their associated on-chip peripherals or in the core. Table 3-5 shows the SFR address space with the SFR mnemonics and reset values. SFR addresses are preceded by “S:”...
Page 59 ADDRESS SPACES Table 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Values CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 CCON CMOD CCAPM0...
Page 60 8XC251SA, SB, SP, SQ USER’S MANUAL The following tables list the mnemonics, names, and addresses of the SFRs: Table 3-6 — Core SFRs Table 3-7 — I/O Port SFRs Table 3-8 — Serial I/O SFRs Table 3-9 — Timer/Counter and Watchdog Timer SFRs Table 3-10 —...
Page 61 ADDRESS SPACES Table 3-8. Serial I/O SFRs Mnemonic Name Address SCON Serial Control S:98H SBUF Serial Data Buffer S:99H SADEN Slave Address Mask S:B9H SADDR Slave Address S:A9H Table 3-9. Timer/Counter and Watchdog Timer SFRs Mnemonic Name Address Timer/Counter 0 Low Byte S:8AH Timer/Counter 0 High Byte S:8CH...
Page 62 8XC251SA, SB, SP, SQ USER’S MANUAL Table 3-10. Programmable Counter Array (PCA) SFRs (Continued) Mnemonic Name Address PCA Timer/Counter Low Byte S:E9H PCA Timer/Counter High Byte S:F9H CCAP0L PCA Compare/Capture Module 0 Low Byte S:EAH CCAP1L PCA Compare/Capture Module 1 Low Byte...
Page 63: Device Configuration
Device Configuration...
Page 65: Configuration Overview
CHAPTER 4 DEVICE CONFIGURATION The 8XC251Sx provides user design flexibility by configuring certain operating features at de- vice reset. These features fall into the following categories: • external memory interface (page mode, address bits, pre-programmed wait states and the address range for RD#, WR#, and PSEN#) •...
Page 66 8XC251SA, SB, SP, SQ USER’S MANUAL For ROM/OTPROM/EPROM devices, user configuration bytes UCONFIG0 and UCONFIG1 can be programmed at the factory or on-site using the procedures provided in Chapter 14, “Pro- gramming and Verifying Nonvolatile Memory.” For devices without ROM/OTPROM/ EPROM, the designer should store configuration information in an eight-byte configuration array located at the highest addresses implemented in external code memory.
Page 67 DEVICE CONFIGURATION 64 Kbytes 8 Kbytes 16 Kbytes 32 Kbytes FFF9H FFF8H 7FF9H 7FF8H 3FF9H 1FF9H 3FF8H 1FF8H 128 Kbytes 256 Kbytes 1:FFF9H 3:FFF9H x :xFFFH 1:FFF8H 3:FFF8H x :xFFEH x :xFFDH Reserved x :xFFCH x :xFFBH x :xFFAH x :xFF9H UCONFIG1 UCONFIG0 x :xFF8H...
Page 68: The Configuration Bits
8XC251SA, SB, SP, SQ USER’S MANUAL Table 4-1. External Addresses for Configuration Array Size of External Address of Address of Address Bus Configuration Array on Configuration Bytes (Bits) External Bus (2) on External Bus (1) FFF8H–FFFFH UCONFIG1: FFF9H UCONFIG0: FFF8H 1FFF8H–1FFFFH...
Page 69: Configuration Byte Location Selector (Ucon)
DEVICE CONFIGURATION CONFIGURATION BYTE LOCATION SELECTOR (UCON) The Configuration Byte Location Selector (UCON) applies only to OTPROM and EPROM prod- ucts. In conjunction with EA#, UCON specifies whether the configuration array is accessed from on-chip memory or external memory. If the UCON bit is clear (e.g., UCON=0), the configuration array is fetched from on-chip nonvol- atile memory at addresses FF:FFF8H to FF:FFFFH.
Page 70 8XC251SA, SB, SP, SQ USER’S MANUAL Address:FF:FFF8H (2) UCONFIG0 (1), (3) UCON WSA1# WSA0# XALE# PAGE# Function Number Mnemonic UCON Configuration Byte Location Selector (OTPROM/EPROM products only): Clearing this bit causes the 8XC251S x to fetch configuration information 87C251Sx from on-chip memory. Leaving this bit unprogrammed (logic 1) causes the 8XC251S x to fetch configuration information from on-chip memory if EA# = 1 or from external memory if EA# = 0.
Page 71 Address. UCONFIG1 is the second-lowest byte of the 8-byte configuration array. As determined by UCON and EA#, the 8XC251SA, SB, SP, SQ fetches configuration information from on-chip nonvolatile memory at addresses FF:FFF8H and FF:FFF9H or from external memory using these same addresses.
Page 72: Configuring The External Memory Interface
8XC251SA, SB, SP, SQ USER’S MANUAL Table 4-2. Memory Signal Selections (RD1:0) P1.7/CEX/ RD1:0 P3.7/RD#/A16 PSEN# Features A17/WCLK Asserted for Asserted for writes to 256-Kbyte external all addresses all memory locations memory P1.7/CEX4/ Asserted for Asserted for writes to 128-Kbyte external...
Page 73: Configuration Bits Rd1:0
DEVICE CONFIGURATION 4.5.2 Configuration Bits RD1:0 The RD1:0 configuration bits (UCONFIG0.3:2) determine the number of external address signals and the address ranges for asserting the read signals PSEN#/RD# and the write signal WR#. These selections offer different ways of addressing external memory. Figures 4-5 and 4-6 show how internal memory maps into external memory for the four values of RD1:0.
Page 74 8XC251SA, SB, SP, SQ USER’S MANUAL This selection provides a 128-Kbyte external address space. The advantage of this selection, in comparison with the 256-Kbyte external memory space with RD1:0 = 00, is the availability of pin P1.7/CEX4/A17/WCLK for general I/O, PCA I/O, and real-time wait clock output. I/O P3.7 is unavailable.
Page 75 DEVICE CONFIGURATION RD1:0 = 10 16 external address bits: Internal Memory with External P0, P2 Read/Write Signals Memory 64 Kbytes Notes: 1. Single read signal PSEN#, WR# 2. P3.7/RD#/A16 functions only as P3.7 00:, 01:, FE:, FF: PSEN#, WR# RD1:0 = 11 External Internal Memory with 16 external address bits:...
Page 76: Rd1:0 = 10 (16 External Address Bits)
8XC251SA, SB, SP, SQ USER’S MANUAL 4.5.2.3 RD1:0 = 10 (16 External Address Bits) For RD1:0 = 10, the 16 external address bits (A15:0 on ports P0 and P2) provide a single 64- Kbyte region in external memory (top of Figure 4-6). This selection provides the smallest exter- nal memory space;...
Page 77: Configuration Bit Xale
DEVICE CONFIGURATION 4.5.3.3 Configuration Bit XALE# Clearing XALE# (UCONFIG0.4) extends the time ALE is asserted from T to 3T . This ac- commodates an address latch that is too slow for the normal ALE signal. Section 13.4.2, “Extend- ing ALE,” shows an external bus cycle with ALE extended. Table 4-3.
Page 78: Selecting Binary Mode Or Source Mode
8XC251SA, SB, SP, SQ USER’S MANUAL Figure 4-7 shows the opcode map for binary mode. Area I (columns 1 through 5 in Table A-6 on page A-4) and area II (columns 6 through F) make up the opcode map for the instructions that originate in the MCS 51 architecture.
Page 79 DEVICE CONFIGURATION A5H Prefix ® MCS 51 MCS 251 Architecture Architecture Architecture A4131-01 Figure 4-7. Binary Mode Opcode Map A5H Prefix ® MCS 251 MCS 51 Architecture Architecture Architecture A4130-01 Figure 4-8. Source Mode Opcode Map 4-15...
Page 80: Mapping On-Chip Code Memory To Data Memory (Emap#)
8XC251SA, SB, SP, SQ USER’S MANUAL MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#) For devices with 16 Kbytes of on-chip code memory (87C251SB, SQ and 83C251SB, SQ), the EMAP# bit (UCONFIG1.0) provides the option of accessing the upper half of on-chip code mem- ory as data memory.
Page 81: Programming
Programming...
Page 83: Source Mode Or Binary Mode Opcodes
CHAPTER 5 PROGRAMMING ® The instruction set for the MCS 251 architecture is a superset of the instruction set for the ® 51 architecture. This chapter describes the addressing modes and summarizes the instruc- tion set, which is divided into data instructions, bit instructions, and control instructions. Appen- dix A, “Instruction Set Reference,”...
Page 84: Data Types
MSB is stored in the lowest byte of the register specified in the instruction. For a description of the register file, see section 3.3, “8XC251SA, SB, SP, SQ Register File.” The code fragment in Figure 5-1 illustrates the storage of words and double words in big endien form.
Page 85 PROGRAMMING Memory 200H 201H 202H 203H MOV WR0,#A3B6H MOV 00:0201H,WR0 MOV DR4,#0000C4D7H Register File Contents of register file and memory after execution A4242-01 Figure 5-1. Word and Double-word Storage in Big Endien Form Table 5-2. Notation for Byte Registers, Word Registers, and Dword Registers Register Register Destination...
Page 86: Addressing Modes
8XC251SA, SB, SP, SQ USER’S MANUAL 5.2.4 Addressing Modes The MCS 251 architecture supports the following addressing modes: • register addressing: The instruction specifies the register that contains the operand. • immediate addressing: The instruction contains the operand. • direct addressing: The instruction contains the operand address.
Page 87: Register Addressing
PROGRAMMING 5.3.1.1 Register Addressing Both architectures address registers directly. • MCS 251 architecture. In the register addressing mode, the operand(s) in a data instruction are in byte registers (R0–R15), word registers (WR0, WR2, ..., WR30), or dword registers (DR0, DR4, ..., DR28, DR56, DR60). •...
Page 88: Indirect
8XC251SA, SB, SP, SQ USER’S MANUAL ® Table 5-3. Addressing Modes for Data Instructions in the MCS 51 Architecture Address Range of Assembly Language Mode Comments Operand Reference R0–R7 – Register (Bank selected by PSW) – Immediate Operand in Instruction...
Page 89 NOTES: These registers are accessible in the memory space as well as in the register file (see section 3.3, “8XC251SA, SB, SP, SQ Register File.” The MCS 251 architecture supports SFRs in locations S:000H–S:1FFH; however, in the 8XC251S x ,...
Page 90: Displacement
8XC251SA, SB, SP, SQ USER’S MANUAL 5.3.1.5 Displacement Several move instructions use displacement addressing to move bytes or words from a source to a destination. Sixteen-bit displacement addressing (@WRj+dis16) accesses indirectly the lowest 64 Kbytes in memory. The base address can be in any word register WRj. The instruction contains a 16-bit signed offset which is added to the base address.
Page 91: Logical Instructions
PROGRAMMING The MCS 251 architecture provides the MUL (multiply) and DIV (divide) instructions for un- signed 8-bit and 16-bit data (Table A-22 on page A-16). Signed multiply and divide are left for the user to manage through a conversion process. The following operations are implemented: eight-bit multiplication: 8 bits ×...
Page 92: Data Transfer Instructions
8XC251SA, SB, SP, SQ USER’S MANUAL 5.3.4 Data Transfer Instructions Data transfer instructions copy data from one register or memory location to another. These in- structions include the move instructions (Table A-24 on page A-19) and the exchange, push, and pop instructions (Table A-25 on page A-22).
Page 93: Bit Instructions
PROGRAMMING BIT INSTRUCTIONS A bit instruction addresses a specific bit in a memory location or SFR. There are four categories of bit instructions: • SETB (Set Bit), CLR (Clear Bit), CPL (Complement Bit). These instructions can set, clear or complement any addressable bit. •...
Page 94: Control Instructions
8XC251SA, SB, SP, SQ USER’S MANUAL Table 5-7 lists the addressing modes for bit instructions and Table A-26 on page A-23 summarizes the bit instructions. “Bit” denotes a bit that is addressed by a new instruction in the MCS 251 ar- chitecture and “bit51”...
Page 95: Addressing Modes For Control Instructions
PROGRAMMING 5.5.1 Addressing Modes for Control Instructions Table 5-8 lists the addressing modes for the control instructions. • Relative addressing: The control instruction provides the target address as an 8-bit signed offset (rel) from the address of the next instruction. •...
Page 96: Conditional Jumps
8XC251SA, SB, SP, SQ USER’S MANUAL 5.5.2 Conditional Jumps The MCS 251 architecture supports bit-conditional jumps, compare-conditional jumps, and jumps based on the value of the accumulator. A bit-conditional jump is based on the state of a bit. In a compare-conditional jump, the jump is based on a comparison of two operands. All condi- tional jumps are relative, and the target address (rel) must be in the current 256-byte block of code.
Page 97: Unconditional Jumps
PROGRAMMING 5.5.3 Unconditional Jumps There are five unconditional jumps. NOP and SJMP jump to addresses relative to the program counter. AJMP, LJMP, and EJMP jump to direct or indirect addresses. • NOP (No Operation) is an unconditional jump to the next instruction. •...
Page 98: Program Status Words
8XC251SA, SB, SP, SQ USER’S MANUAL RETI (Return from Interrupt) provides a return from an interrupt service routine. The operation of RETI depends on the INTR bit in the UCONFIG1 or CONFIG1 configuration byte: • For INTR = 0, an interrupt pushes the two lower bytes of the PC onto the stack in the following order: PC.7:0, PC.15:8.
Page 99 PROGRAMMING Table 5-10. The Effects of Instructions on the PSW and PSW1 Flags Flags Affected (1), (5) Instruction Type Instruction AC (2) ADD, ADDC, SUB, SUBB, CMP INC, DEC Arithmetic MUL, DIV (3) ANL, ORL, XRL, CLR A, CPL A, RL, RR, SWAP Logical RLC, RRC, SRL, SLL, SRA (4)
Page 100 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:D0H Reset State: 0000 0000B Function Number Mnemonic Carry Flag: The carry flag is set by an addition instruction (ADD, ADDC) if there is a carry out of the MSB. It is set by a subtraction (SUB, SUBB) or compare (CMP) if a borrow is needed for the MSB.
Page 101 PROGRAMMING Address: S:D1H PSW1 Reset State: 0000 0000B — Function Number Mnemonic Carry Flag: Identical to the CY bit in the PSW register (Figure 5-2). Auxiliary Carry Flag: Identical to the AC bit in the PSW register (Figure 5-2). Negative Flag: This bit is set if the result of the last logical or arithmetic operation was negative (i.e., bit 15 = 1).
Page 103: Interrupt System
Interrupt System...
Page 105: Overview
CHAPTER 6 INTERRUPT SYSTEM OVERVIEW The 8XC251Sx, like other control-oriented computer architectures, employs a program interrupt method. This operation branches to a subroutine and performs some service in response to the interrupt. When the subroutine completes, execution resumes at the point where the interrupt oc- curred.
Page 106 8XC251SA, SB, SP, SQ USER’S MANUAL Interrupt Enable Priority Enable Highest Priority Interrupt INT0# Timer 0 INT1# Timer 1 Counter Overflow ECCF x Match or CCF x Capture Receive Transmit Timer 2 T2EX EXF2 Lowest Priority Interrupt A4149-01 Figure 6-1. Interrupt Control System...
Page 107: 8Xc251Sa, Sb, Sp, Sq Interrupt Sources
Used in conjunction with IPL0. NOTE: Other special function registers are described in their respective chapters. 8XC251SA, SB, SP, SQ INTERRUPT SOURCES Figure 6-1 illustrates the interrupt control system. The 8XC251Sx has eight interrupt sources; seven maskable sources and the TRAP instruction (always enabled). The maskable sources in- clude two external interrupts (INT0# and INT1#), three timer interrupts (timers 0, 1, and 2), one programmable counter array (PCA) interrupt, and one serial port interrupt.
Page 108: Timer Interrupts
8XC251SA, SB, SP, SQ USER’S MANUAL Table 6-3. Interrupt Control Matrix Global Timer Serial Timer Timer Interrupt Name INT1# INT0# Enable Port Bit Name in IE0 Register Interrupt Priority- Within-Level (7 = Low Priority, 1 = High Priority) Bit Names in:...
Page 109: Programmable Counter Array (Pca) Interrupt
INTERRUPT SYSTEM PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT The programmable counter array (PCA) interrupt is generated by the logical OR of five event flags (CCFx) and the PCA timer overflow flag (CF) in the CCON register (see Figure 9-8 on page 9-14).
Page 110 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:A8H Reset State: 0000 0000B Function Number Mnemonic Global Interrupt Enable: Setting this bit enables all interrupts that are individually enabled by bits 0–6. Clearing this bit disables all interrupts, except the TRAP interrupt, which is always enabled.
Page 111: Interrupt Priorities
INTERRUPT SYSTEM INTERRUPT PRIORITIES Each of the seven 8XC251Sx interrupt sources may be individually programmed to one of four priority levels. This is accomplished with the IPH0.x/IPL0.x bit pairs in the interrupt priority high (IPH0) and interrupt priority low (IPL0) registers (Figures 6-3 and 6-4 on page 6-8). Specify the priority level as shown in Table 6-4 using IPH0.x as the MSB and IPL0.x as the LSB.
Page 112 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:B7H IPH0 Reset State: X000 0000B — IPH0.6 IPH0.5 IPH0.4 IPH0.3 IPH0.2 IPH0.1 IPH0.0 Function Number Mnemonic — Reserved. The value read from this bit is indeterminate. Write a “0” to this bit.
Page 113: Interrupt Processing
INTERRUPT SYSTEM INTERRUPT PROCESSING Interrupt processing is a dynamic operation that begins when a source requests an interrupt and lasts until the execution of the first instruction in the interrupt service routine (see Figure 6-5). Response time is the amount of time between the interrupt request and the resulting break in the current instruction stream.
Page 114: Minimum Fixed Interrupt Time
8XC251SA, SB, SP, SQ USER’S MANUAL 6.7.1 Minimum Fixed Interrupt Time All interrupts are sampled or polled every four state times (see Figure 6-5). Two of eight inter- rupts are latched and polled per state time within any given four state time window. One addition- al state time is required for a context switch request.
Page 115 INTERRUPT SYSTEM time is five states for internal interrupts and six states for external interrupts. External interrupts must remain active for at least five state times to guarantee interrupt recognition when the request occurs immediately after a sample has been taken (i.e., requested in the second half of a sample state time). If the external interrupt goes active one state after the sample state, the pin is not resampled for another three states.
Page 116: Computation Of Worst-Case Latency With Variables
8XC251SA, SB, SP, SQ USER’S MANUAL Response Time = 4 State Time INT0# Sample INT0# Request Ten State Push PC Instruction A4154-02 Figure 6-7. Response Time Example #2 6.7.2.2 Computation of Worst-case Latency With Variables Worst-case latency calculations assume that the longest 8XC251Sx instruction used in the pro- gram must fully execute prior to a context switch.
Page 117: Latency Calculations
INTERRUPT SYSTEM Table 6-6. Interrupt Latency Variables External INT0#, >64K External External External External Page Memory Variable INT1#, Jump to Stack Stack Stack Execution Mode Wait T2EX ISR (1) <64K (1) >64K (1) Wait State State Number 1 per 1 per States bus cycle bus cycle...
Page 118: Blocking Conditions
8XC251SA, SB, SP, SQ USER’S MANUAL 6.7.2.4 Blocking Conditions If all enable and priority requirements have been met, a single prioritized interrupt request at a time generates a vector cycle to an interrupt service routine (refer to the CALL instructions in Ap- pendix A, “Instruction Set Reference”).
Page 119: Isrs In Process
INTERRUPT SYSTEM 6.7.3 ISRs in Process ISR execution proceeds until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is completed. The RETI instruction in the ISR pops PC address bytes off the stack (as well as PSW1 for INTR = 1) and execution resumes at the suspend- ed instruction stream.
Page 121: Input/Output Ports
Input/Output Ports...
Page 123: Input/Output Port Overview
CHAPTER 7 INPUT/OUTPUT PORTS INPUT/OUTPUT PORT OVERVIEW The 8XC251Sx uses input/output (I/O) ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations (see Chapter 13, “External Memory Interface”); others allow for alternate functions. All four 8XC251Sx I/O ports are bidirectional.
Page 124: I/O Configurations
8XC251SA, SB, SP, SQ USER’S MANUAL I/O CONFIGURATIONS Each port SFR operates via type-D latches, as illustrated in Figure 7-1 for ports 1 and 3. A CPU “write to latch” signal initiates transfer of internal bus data into the type-D latch. A CPU “read latch”...
Page 125 INPUT/OUTPUT PORTS Alternate Internal Read Output Pullup Latch Function P3. x Internal P3. x Latch Write to Latch Read Alternate Input Function A2239-01 Figure 7-1. Port 1 and Port 3 Structure Address/ Read Data Control Latch P0. x Internal P0. x Latch Write to Latch...
Page 126 8XC251SA, SB, SP, SQ USER’S MANUAL Address Control Internal Read Pullup Latch P2. x Internal P2. x Latch Write to Latch Read A2240-01 Figure 7-3. Port 2 Structure When port 0 and port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line.
Page 127: Read-Modify-Write Instructions
INPUT/OUTPUT PORTS READ-MODIFY-WRITE INSTRUCTIONS Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data, and then rewrite the latch. These are called “read-modify-write” in- structions. Below is a complete list of these special instructions. When the destination operand is a port, or a port bit, these instructions read the latch rather than the pin: (logical AND, e.g., ANL P1, A) (logical OR, e.g., ORL P2, A)
Page 128: Quasi-Bidirectional Port Operation
If logical zero is subsequently written to a port latch, it can be returned to input conditions by a logical one written to the latch. For additional electrical information, refer to the 8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller Datasheet.
Page 129: Port Loading
INPUT/OUTPUT PORTS 2 Osc. Periods Port From Port Latch Input Data Read Port Pin A2242-01 Figure 7-4. Internal Pullup Configurations PORT LOADING Output buffers of port 1, port 2, and port 3 can each sink 1.6 mA at logic zero (see V specifica- tions in the 8XC251Sx data sheet).
Page 130 8XC251SA, SB, SP, SQ USER’S MANUAL The 8XC251Sx CPU writes FFH to the P0 register for all external memory bus cycles. This over- writes previous information in P0. In contrast, the P2 register is unmodified for external bus cy- cles. When address bits or data bits are not on the port 2 pins, the bit values in P2 appear on the port 2 pins.
Page 131 INPUT/OUTPUT PORTS Table 7-2. Instructions for External Data Moves Bus Width Instructions MOVX @Ri; MOV @Rm; MOV dir8 MOVX @DPTR; MOV @WRj; MOV @WRj+dis; MOV dir16 MOV @DRk; MOV @DRk+dis MOV @DRk; MOV @DRk+dis NOTE Avoid MOV P0 instructions for external memory accesses. These instructions can corrupt input code bytes at port 0.
Page 133: Timer/Counters And Watchdog Timer
Timer/Counters and Watchdog Timer...
Page 135: Timer/Counter Overview
CHAPTER 8 TIMER/COUNTERS AND WATCHDOG TIMER This chapter describes the timer/counters and the watchdog timer (WDT) included as peripherals on the 8XC251Sx. When operating as a timer, a timer/counter runs for a programmed length of time, then issues an interrupt request. When operating as a counter, a timer/counter counts nega- tive transitions on an external pin.
Page 136 8XC251SA, SB, SP, SQ USER’S MANUAL Table 8-1. Timer/Counter and Watchdog Timer SFRs Mnemonic Description Address Timer 0 Timer Registers. Used separately as 8-bit counters or in cascade S:8AH as a 16-bit counter. Counts an internal clock signal with frequency F S:8CH (timer operation) or an external input (event counter operation).
Page 137: Timer 0
TIMER/COUNTERS AND WATCHDOG TIMER For timer operation (C/Tx# = 0), the timer register counts the divided-down system clock. The timer register is incremented once every peripheral cycle, i.e., once every six states (see section 2.2.2, “Clock and Reset Unit”). Since six states equals 12 clock cycles, the timer clock rate is /12.
Page 138: Mode 0 (13-Bit Timer)
8XC251SA, SB, SP, SQ USER’S MANUAL For normal timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the se- lected input. Setting GATE0 and TR0 allows external pin INT0# to control timer operation. This setup can be used to make pulse width measurements. See section 8.5.2, “Pulse Width Measure- ments.”...
Page 139: Mode 2 (8-Bit Timer With Auto-Reload)
TIMER/COUNTERS AND WATCHDOG TIMER 8.3.3 Mode 2 (8-bit Timer With Auto-reload) Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from the TH0 register (Figure 8-3). TL0 overflow sets the timer overflow flag (TF0) in the TCON register and reloads TL0 with the contents of TH0, which is preset by software.
Page 140 8XC251SA, SB, SP, SQ USER’S MANUAL Timer 1 is controlled by the four high-order bits of the TMOD register (Figure 8-5) and bits 7, 6, 3, and 2 of the TCON register (Figure 8-6). The TMOD register selects the method of timer gating (GATE1), timer or counter operation (T/C1#), and mode of operation (M11 and M01).
Page 141 TIMER/COUNTERS AND WATCHDOG TIMER Address: S:89H TMOD Reset State: 0000 0000B GATE1 C/T1# GATE0 C/T0# Function Number Mnemonic GATE1 Timer 1 Gate: When GATE1 = 0, run control bit TR1 gates the input signal to the timer register. When GATE1 = 1 and TR1 = 1, external signal INT1 gates the timer input.
Page 142 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:88H TCON Reset State: 0000 0000B Function Number Mnemonic Timer 1 Overflow Flag: Set by hardware when the timer 1 register overflows. Cleared by hardware when the processor vectors to the interrupt routine.
Page 143: Mode 0 (13-Bit Timer)
TIMER/COUNTERS AND WATCHDOG TIMER 8.4.1 Mode 0 (13-bit Timer) Mode 0 configures timer 0 as a 13-bit timer, which is set up as an 8-bit timer (TH1 register) with a modulo-32 prescalar implemented with the lower 5 bits of the TL1 register (Figure 8-2). The upper 3 bits of the TL1 register are ignored.
Page 144: Pulse Width Measurements
8XC251SA, SB, SP, SQ USER’S MANUAL Enter an eight-bit reload value (n ) in register TH0. This can be the same as n different, depending on the application. Set the TR0 bit in the TCON register (Figure 8-6) to start the timer. Timer overflow occurs...
Page 145: Capture Mode
TIMER/COUNTERS AND WATCHDOG TIMER Timer 2 provides the following operating modes: capture mode, auto-reload mode, baud rate gen- erator mode, and programmable clock-out mode. Select the operating mode with T2MOD and TCON register bits as shown in Table 8-3 on page 8-15. Auto-reload is the default mode. Setting RCLK and/or TCLK selects the baud rate generator mode.
Page 146: Auto-Reload Mode
8XC251SA, SB, SP, SQ USER’S MANUAL 8.6.2 Auto-reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. The timer operates an as an up counter or as an up/down counter, as determined by the down counter enable bit (DCEN).
Page 147: Up/Down Counter Operation
TIMER/COUNTERS AND WATCHDOG TIMER 8.6.2.2 Up/Down Counter Operation When DCEN = 1, timer 2 operates as an up/down counter (Figure 8-9). External pin T2EX con- trols the direction of the count (Table 8-2 on page 8-3). When T2EX is high, timer 2 counts up. The timer overflow occurs at FFFFH which sets the timer 2 overflow flag (TF2) and generates an interrupt request.
Page 148: Baud Rate Generator Mode
8XC251SA, SB, SP, SQ USER’S MANUAL 8.6.3 Baud Rate Generator Mode This mode configures timer 2 as a baud rate generator for use with the serial port. Select this mode by setting the RCLK and/or TCLK bits in T2CON. See Table 8-3. For details regarding this mode of operation, refer to section 10.6, “Baud Rates.”...
Page 149 TIMER/COUNTERS AND WATCHDOG TIMER XTAL1 (8 Bits) (8 Bits) RCAP2H RCAP2L C/T2# T2OE Interrupt Request T2EX EXF2 EXEN2 A4116-02 Figure 8-10. Timer 2: Clock Out Mode Table 8-3. Timer 2 Modes of Operation RCLK OR TCLK CP/RL2# T2OE Mode (in T2CON) (in T2CON) (in T2MOD) Auto-reload Mode...
Page 150: Watchdog Timer
8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:C9H T2MOD Reset State: XXXX XX00B — — — — — — T2OE DCEN Function Number Mnemonic — Reserved: The values read from these bits are indeterminate. Write zeros to these bits. T2OE...
Page 151 TIMER/COUNTERS AND WATCHDOG TIMER Address: S:C8H T2CON Reset State: 0000 0000B EXF2 RCLK TCLK EXEN2 C/T2# CP/RL2# Function Number Mnemonic Timer 2 Overflow Flag: Set by timer 2 overflow. Must be cleared by software. TF2 is not set if RCLK = 1 or TCLK = 1. EXF2 Timer 2 External Flag: If EXEN2 = 1, capture or reload caused by a negative transition on T2EX...
Page 152: Using The Wdt
8XC251SA, SB, SP, SQ USER’S MANUAL 8.7.2 Using the WDT To use the WDT to recover from software malfunctions, the user program should control the WDT as follows: Following device reset, write the two-byte sequence 1EH-E1H to the WDTRST register to enable the WDT.
Page 153: Programmable Counter Array
Programmable Counter Array...
Page 155: Pca Description
CHAPTER 9 PROGRAMMABLE COUNTER ARRAY This chapter describes the programmable counter array (PCA), an on-chip peripheral of the 8XC251Sx that performs a variety of timing and counting operations, including pulse width mod- ulation (PWM). The PCA provides the capability for a software watchdog timer (WDT). PCA DESCRIPTION The programmable counter array (PCA) consists of a 16-bit timer/counter and five 16-bit com- pare/capture modules.
Page 156: Alternate Port Usage
8XC251SA, SB, SP, SQ USER’S MANUAL 9.1.1 Alternate Port Usage PCA modules 3 and 4 share port pins with the real-time wait state and address functions as fol- lows: • PCA module 3 — P1.6/CEX3/WAIT# • PCA module 4 — P1.7/CEX4/A17/WCLK When the real-time wait state functions are enabled (using the WCON register), the correspond- ing PCA modules are automatically disabled.
Page 157 PROGRAMMABLE COUNTER ARRAY Setting the run control bit (CR in the CCON register) turns the PCA timer/counter on, if the out- put of the NAND gate (Figure 9-1) equals logic 1. The PCA timer/counter continues to operate during idle mode unless the CIDL bit of the CMOD register is set. The CPU can read the contents of the CH and CL registers at any time.
Page 158 8XC251SA, SB, SP, SQ USER’S MANUAL Table 9-1. PCA Special Function Registers (SFRs) Mnemonic Description Address PCA Timer/Counter. These registers serve as a common 16-bit timer or S:E9H event counter for the five compare/capture modules. Counts F /12, S:F9H /4, timer 0 overflow, or the external signal on P1.2/ECI, as selected by CMOD.
Page 159: Pca Compare/Capture Modules
PROGRAMMABLE COUNTER ARRAY PCA COMPARE/CAPTURE MODULES Each compare/capture module is made up compare/capture register pair (CCAPxH/CCAPxL), a 16-bit comparator, and various logic gates and signal transition selectors. The registers store the time or count at which an external event occurred (capture) or at which an action should occur (comparison).
Page 160 8XC251SA, SB, SP, SQ USER’S MANUAL To program a compare/capture module for the 16-bit capture mode, program the CAPPx and CAPNx bits in the module’s CCAPMx register as follows: • To trigger the capture on a positive transition, set CAPPx and clear CAPNx.
Page 161: Compare Modes
PROGRAMMABLE COUNTER ARRAY 9.3.2 Compare Modes The compare function provides the capability for operating the five modules as timers, event counters, or pulse width modulators. Four modes employ the compare function: 16-bit software timer mode, high-speed output mode, WDT mode, and PWM mode. In the first three of these, the compare/capture module continuously compares the 16-bit PCA timer/counter value with the 16- bit value pre-loaded into the module’s CCAPxH/CCAPxL register pair.
Page 162: High-Speed Output Mode
8XC251SA, SB, SP, SQ USER’S MANUAL Compare/Capture PCA Timer/Counter Module Count Input CCAP x H CCAP x L (8 Bits) (8 Bits) (8 Bits) (8 Bits) Toggle Match 16-Bit CEX x Comparator Interrupt Request Enable CCF x CCON Enable ECOM x...
Page 163: Pca Watchdog Timer Mode
PROGRAMMABLE COUNTER ARRAY The user also has the option of generating an interrupt request when the match occurs by setting the corresponding interrupt enable bit (ECCFx in the CCAPMx register). Since hardware does not clear the compare/capture flag when the interrupt is processed, the user must clear the flag in soft- ware.
Page 164 8XC251SA, SB, SP, SQ USER’S MANUAL The PCA WDT generates a reset signal each time a match occurs. To hold off a PCA WDT reset, the user has three options: • periodically change the comparison value in CCAP4H/CCAP4L so a match never occurs •...
Page 165: Pulse Width Modulation Mode
PROGRAMMABLE COUNTER ARRAY 9.3.6 Pulse Width Modulation Mode The five PCA comparator/capture modules can be independently programmed to function as pulse width modulators (Figure 9-5). The modulated output, which has a pulse width resolution of eight bits, is available at the CEXx pin. The PWM output can be used to convert digital data to an analog signal with simple external circuitry.
Page 166 8XC251SA, SB, SP, SQ USER’S MANUAL The value in CCAPxL determines the duty cycle of the current period. The value in CCAPxH de- termines the duty cycle of the following period. Changing the value in CCAPxL over time mod- ulates the pulse width. As depicted in Figure 9-6, the 8-bit value in CCAPxL can vary from 0 (100% duty cycle) to 255 (0.4% duty cycle).
Page 167 PROGRAMMABLE COUNTER ARRAY Address: S:D9H CMOD Reset State: 00XX X000B CIDL WDTE — — — CPS1 CPS0 Function Number Mnemonic CIDL PCA Timer/Counter Idle Control: CIDL = 1 disables the PCA timer/counter during idle mode. CIDL = 0 allows the PCA timer/counter to run during idle mode. WDTE Watchdog Timer Enable: WDTE = 1 enables the watchdog timer output on PCA module 4.
Page 168 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:D8H CCON Reset State: 00X0 0000B — CCF4 CCF3 CCF2 CCF1 CCF0 Function Number Mnemonic PCA Timer/Counter Overflow Flag: Set by hardware when the PCA timer/counter rolls over. This generates an interrupt request if the ECF interrupt enable bit in CMOD is set. CF can be set by hardware or software but can be cleared only by software.
Page 169 PROGRAMMABLE COUNTER ARRAY Address: CCAPM0 S:DAH CCAPM x ( x = 0–4) CCAPM1 S:DBH CCAPM2 S:DCH CCAPM3 S:DDH CCAPM4 S:DEH Reset State: X000 0000B — ECOM x CAPP x CAPN x MAT x TOG x PWM x ECCF x Function Number Mnemonic —...
Page 171: Serial I/O Port
Serial I/O Port...
Page 173: Overview
CHAPTER 10 SERIAL I/O PORT The serial input/output port supports communication with modems and other external peripheral devices. This chapter provides instructions for programming the serial port and generating the se- rial I/O baud rates with timer 1 and timer 2. 10.1 OVERVIEW The serial I/O port provides both synchronous and asynchronous communication modes.
Page 174 8XC251SA, SB, SP, SQ USER’S MANUAL Table 10-2. Serial Port Special Function Registers Mnemonic Description Address SBUF Serial Buffer. Two separate registers comprise the SBUF register. Writing to SBUF loads the transmit buffer; reading SBUF accesses the receive buffer. SCON Serial Port Control.
Page 175 SERIAL I/O PORT The serial port control (SCON) register (Figure 10-2) configures and controls the serial port. Address: SCON Reset State: 0000 0000B FE/SM0 Function Number Mnemonic Framing Error Bit: To select this function, set the SMOD0 bit in the PCON register. Set by hardware to indicate an invalid stop bit.
Page 176: Modes Of Operation
8XC251SA, SB, SP, SQ USER’S MANUAL Transmit Interrupt Flag Bit: Set by the transmitter after the last data bit is transmitted. Cleared by software. Receive Interrupt Flag Bit: Set by the receiver after the last data bit of a frame has been received.
Page 177: Reception (Mode 0)
SERIAL I/O PORT Transmit S3P1 S6P1 Write to SBUF S6P2 Shift S6P2 S6P2 S6P2 S6P2 S6P2 S6P2 S1P1 Receive S3P1 S6P1 Write to Set REN, Clear RI SCON S6P2 Shift S6P2 S6P2 S6P2 S6P2 S6P2 S6P2 S5P2 S1P1 A4124-02 Figure 10-3. Mode 0 Timing 10.2.1.2 Reception (Mode 0) To start a reception in mode 0, write to the SCON register.
Page 178: Asynchronous Modes (Modes 1, 2, And 3)
8XC251SA, SB, SP, SQ USER’S MANUAL 10.2.2 Asynchronous Modes (Modes 1, 2, and 3) The serial port has three asynchronous modes of operation. • Mode 1. Mode 1 is a full-duplex, asynchronous mode. The data frame (Figure 10-4) consists of 10 bits: one start bit, eight data bits, and one stop bit. Serial data is transmitted on the TXD pin and received on the RXD pin.
Page 179: Framing Bit Error Detection (Modes 1, 2, And 3)
SERIAL I/O PORT 10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3) Framing bit error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set the SMOD0 bit in the PCON register (Figure 12-1 on page 12-2). When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
Page 180: Given Address
8XC251SA, SB, SP, SQ USER’S MANUAL Implemented in hardware, automatic address recognition enhances the multiprocessor communi- cation feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address does the receiver set the RI bit in the SCON register to generate an interrupt.
Page 181: Broadcast Address
SERIAL I/O PORT The SADEN byte is selected so that each slave may be addressed separately. For Slave A, bit 0 (the LSB) is a don't-care bit; for Slaves B and C, bit 0 is a 1. To communicate with Slave A only, the master must send an address where bit 0 is clear (e.g., 1111 0000).
Page 182: Reset Addresses
8XC251SA, SB, SP, SQ USER’S MANUAL 10.5.3 Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00H, i.e., the given and broadcast addresses are XXXX XXXX (all don't-care bits). This ensures that the serial port is backwards- ®...
Page 183: Timer 1 Generated Baud Rates (Modes 1 And 3)
SERIAL I/O PORT 10.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3) Timer 1 is the default baud rate generator for the transmitter and the receiver in modes 1 and 3. The baud rate is determined by the timer 1 overflow rate and the value of SMOD, as shown in the following formula: Timer 1 Overflow Rate SMOD1...
Page 184: Timer 2 Generated Baud Rates (Modes 1 And 3)
8XC251SA, SB, SP, SQ USER’S MANUAL Table 10-4. Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3 Timer 1 Oscillator Baud Frequency SMOD1 Rate Reload C/T# Mode Value 62.5 Kbaud (Max) 12.0 MHz 19.2 Kbaud 11.059 MHz 9.6 Kbaud...
Page 185 SERIAL I/O PORT You may configure timer 2 as a timer or a counter. In most applications, it is configured for timer operation (i.e., the C/T2# bit is clear in the T2CON register). Table 10-5. Selecting the Baud Rate Generator(s) RCLCK TCLCK Receiver...
Page 186 8XC251SA, SB, SP, SQ USER’S MANUAL Note that timer 2 increments every state time (2T ) when it is in the baud rate generator mode. In the baud rate formula that follows, “RCAP2H, RCAP2L” denotes the contents of RCAP2H and RCAP2L taken as a 16-bit unsigned integer:...
Page 187: Minimum Hardware Setup
Minimum Hardware Setup...
Page 189 CHAPTER 11 MINIMUM HARDWARE SETUP ® This chapter discusses the basic operating requirements of the MCS 251 microcontroller and de- scribes a minimum hardware setup. Topics covered include power, ground, clock source, and de- vice reset. For parameter values, refer to the device data sheet. 11.1 MINIMUM HARDWARE SETUP Figure 11-1 shows a minimum hardware setup that employs the on-chip oscillator for the system clock and provides power-on reset.
Page 190: Electrical Environment
8XC251SA, SB, SP, SQ USER’S MANUAL 11.2 ELECTRICAL ENVIRONMENT The 8XC251Sx is a high-speed CHMOS device. To achieve satisfactory performance, its operat- ing environment should accommodate the device signal waveforms without introducing distor- tion or noise. Design considerations relating to device performance are discussed in this section.
Page 191: Clock Sources
MINIMUM HARDWARE SETUP 11.3 CLOCK SOURCES The 8XC251Sx can obtain the system clock signal from an external clock source (Figure 11-3) or it can generate the clock signal using the on-chip oscillator amplifier and external capacitors and resonator (Figure 11-2). 11.3.1 On-chip Oscillator (Crystal) This clock source uses an external quartz crystal connected from XTAL1 to XTAL2 as the fre- quency-determining element (Figure 11-2).
Page 192: On-Chip Oscillator (Ceramic Resonator)
8XC251SA, SB, SP, SQ USER’S MANUAL For a more in-depth discussion of crystal specifications, ceramic resonators, and the selection of C1 and C2 see Applications Note AP-155, “Oscillators for Microcontrollers,” in the Embedded Applications handbook. 11.3.2 On-chip Oscillator (Ceramic Resonator) In cost-sensitive applications, you may choose a ceramic resonator instead of a crystal.
Page 193: Reset
MINIMUM HARDWARE SETUP For external clock drive requirements, see the device data sheet. Figure 11-4 shows the clock drive waveform. The external clock source must meet the minimum high and low times (T CHCX and T ) and the maximum rise and fall times (T and T ) to minimize the effect of ex- CLCX...
Page 194: Externally Initiated Resets
8XC251SA, SB, SP, SQ USER’S MANUAL The power off flag (POF) in the PCON register indicates whether a reset is a warm start or a cold start. A cold start reset (POF = 1) is a reset that occurs after power has been off or V has fallen below 3 V, so the contents of volatile memory are indeterminate.
Page 195: Power-On Reset
MINIMUM HARDWARE SETUP While the RST pin is high ALE, PSEN#, and the port pins are weakly pulled high. The first ALE occurs 32T after the reset signal goes low. For this reason, other devices can not be synchro- nized to the internal timings of the 8XC251Sx. NOTE Externally driving the ALE and/or PSEN# pins to 0 during the reset routine may cause the device to go into an indeterminate state.
Page 196 8XC251SA, SB, SP, SQ USER’S MANUAL ≥ 64 T XTAL Internal Reset Routine PSEN# First ALE A4103-01 Figure 11-5. Reset Timing Sequence 11-8...
Page 197: Special Operating Modes
Special Operating Modes...
Page 199: General
CHAPTER 12 SPECIAL OPERATING MODES This chapter describes the power control (PCON) register and three special operating modes: idle, powerdown, and on-circuit emulation (ONCE). 12.1 GENERAL The idle and powerdown modes are power reduction modes for use in applications where power consumption is a concern.
Page 200 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:87H PCON Reset State: 00XX 0000B SMOD1 SMOD0 — Function Number Mnemonic SMOD1 Double Baud Rate Bit: When set, doubles the baud rate when timer 1 is used and mode 1, 2, or 3 is selected in the SCON register.
Page 201 SPECIAL OPERATING MODES Table 12-1. Pin Conditions in Various Modes Program PSEN# Port 0 Port 1 Port 2 Port 3 Mode Memory Pins Pins Pins Pins Reset Don’t Care Weak High Weak High Floating Weak High Weak High Weak High Idle Internal Data...
Page 202: Idle Mode
8XC251SA, SB, SP, SQ USER’S MANUAL 12.3 IDLE MODE Idle mode is a power reduction mode that reduces power consumption to about 40% of normal. In this mode, program execution halts. Idle mode freezes the clocks to the CPU at known states while the peripherals continue to be clocked (Figure 12-2).
Page 203: Exiting Idle Mode
SPECIAL OPERATING MODES 12.3.2 Exiting Idle Mode There are two ways to exit idle mode: • Generate an enabled interrupt. Hardware clears the PCON register IDL bit which restores the clocks to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated idle mode.
Page 204: Entering Powerdown Mode
8XC251SA, SB, SP, SQ USER’S MANUAL 12.4.1 Entering Powerdown Mode To enter powerdown mode, set the PCON register PD bit. The 8XC251Sx enters the power-down mode upon execution of the instruction that sets the PD bit. The instruction that sets the PD bit is the last instruction executed.
Page 205: On-Circuit Emulation (Once) Mode
SPECIAL OPERATING MODES 12.5 ON-CIRCUIT EMULATION (ONCE) MODE The on-circuit emulation (ONCE) mode permits external testers to test and debug 8XC251Sx- based systems without removing the chip from the circuit board. A clamp-on emulator or test CPU is used in place of the 8XC251Sx which is electrically isolated from the system. 12.5.1 Entering ONCE Mode To enter the ONCE mode: Assert RST to initiate a device reset.
Page 207: External Memory Interface
External Memory Interface...
Page 209: Overview
P0 in nonpage mode and with A15:8 on P2 in page mode. Table 13-1 describes the external memory interface signals. The address and data signals (AD7:0 on port 0 and A15:8 on port 2) are defined for nonpage mode. RAM/ RAM/ 8XC251SA 8XC251SA EPROM/ EPROM/ 8XC251SB...
Page 210 8XC251SA, SB, SP, SQ USER’S MANUAL Table 13-1. External Memory Interface Signals Signal Alternate Type Description Name Function Address Line 17. P1.7/CEX4/WCLK Address Line 16. See RD#. P3.7/RD# A15:8 † Address Lines. Upper address for external bus (non-page mode). P2.7:0 AD7:0 †...
Page 211: External Bus Cycles
EXTERNAL MEMORY INTERFACE 13.2 EXTERNAL BUS CYCLES The section describes the bus cycles the 8XC251Sx executes to fetch code, read data, and write data in external memory. Both page mode and nonpage mode are described and illustrated. For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information.
Page 212 8XC251SA, SB, SP, SQ USER’S MANUAL 13.2.2 Nonpage Mode Bus Cycles In nonpage mode, the external bus structure is the same as for MCS 51 microcontrollers. The up- per address bits (A15:8) are on port 2, and the lower address bits (A7:0) are multiplexed with the data (D7:0) on port 0.
Page 213: Page Mode Bus Cycles
EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 XTAL A7:0 D7:0 A17/A16/P2 A17/A16/A15:8 A2808-03 Figure 13-4. External Data Write (Nonpage Mode) 13.2.3 Page Mode Bus Cycles Page mode increases performance by reducing the time for external code fetches. Under certain conditions the controller fetches an instruction from external memory in one state time instead of two (Table 13-2).
Page 214 8XC251SA, SB, SP, SQ USER’S MANUAL Figure 13-5 shows the two types of external bus cycles for code fetches in page mode. The page- miss cycle is the same as a code fetch cycle in nonpage mode (except D7:0 is multiplexed with A15:8 on P2.).
Page 215 EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 XTAL RD#/PSEN# A17/A16/P0 A17/A16/A7:0 A15:8 D7:0 A2811-04 Figure 13-6. External Data Read (Page Mode) State 1 State 2 State 3 XTAL A17/A16/P0 A17/A16/A7:0 A15:8 D7:0 A2810-03 Figure 13-7. External Data Write (Page Mode) 13-7...
Page 216: Wait States
WCON special function register. See section 13.5, “External Bus Cycles with Real-time Wait States.” In addition, the 8XC251SA, SB, SP, SQ device can be configured at reset to add wait states to external bus cycles by extending the ALE or RD#/WR#/PSEN# pulses. See section 4.5.3, “Wait State Configuration Bits.”...
Page 217 EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 XTAL RD#/PSEN# A7:0 D7:0 A17/A16/P2 A17/A16/A15:8 A2812-04 Figure 13-8. External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) State 1 State 2 State 3 State 4 XTAL A7:0 D7:0 A17/A16/P2 A17/A16/A15:8 A4174-02 Figure 13-9.
Page 218: Extending Ale
Figure 13-10. External Code Fetch (Nonpage Mode, One ALE Wait State) 13.5 EXTERNAL BUS CYCLES WITH REAL-TIME WAIT STATES In addition to fixed-length wait states such as RD#/WR#/PSEN# and ALE, the 8XC251SA, SB, SP, SQ offers a real-time wait state. The programmer can dynamically adjust the delay of the real- time wait state by means of registers.
Page 219 EXTERNAL MEMORY INTERFACE Address: S:A7H WCON Reset State: XXXX XX00B — — — — — — RTWCE RTWE Function Number Mnemonic — Reserved: The values read from these bits are indeterminate. Write “0” to these bits. RTWCE Real-time WAIT CLOCK enable. Write a ‘1’ to this bit to enable the WAIT CLOCK on port 1.7 (WCLK).
Page 220: Real-Time Wait# Enable (Rtwe)
Use of PCA module 3 may conflict with your design. Do not use CEX3 inter- changeably with the WAIT# signal on the port 1.3 input. Setup and hold times are illustrated in the 8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller Datasheet. 13.5.2 Real-time WAIT CLOCK Enable (RTWCE) The real-time WAIT CLOCK output is driven at port 1.7 (WCLK) by writing a logical ‘1’...
Page 221 EXTERNAL MEMORY INTERFACE State 1 State 2 State 3 State 1 (next cycle) WCLK RD#/PSEN# RD#/PSEN# stretched WAIT# A0-A7 D0-D7 stretched A0-A7 A8-A15 stretched A8-A15 A5007-01 Figure 13-12. External Code Fetch/Data Read (Nonpage Mode, RT Wait State) State 1 State 2 State 3 State 4 WCLK...
Page 222 8XC251SA, SB, SP, SQ USER’S MANUAL State 1 State 2 State 3 State 1 (next cycle) WCLK RD#/PSEN# RD#/PSEN# stretched WAIT# A8-A15 D0-D7 stretched A8-A15 A0-A7 stretched A0-A7 A5008-01 Figure 13-14. External Data Read (Page Mode, RT Wait State) State 1...
Page 223 EXTERNAL MEMORY INTERFACE 13.6 CONFIGURATION BYTE BUS CYCLES If EA# = 0, devices obtain configuration information from a configuration array in external mem- ory. This section describes the bus cycles executed by the reset routine to fetch user configuration bytes from external memory. Configuration bytes are discussed in Chapter 4, “Device Configu- ration.”...
Page 224: Port 0 And Port 2 Status
8XC251SA, SB, SP, SQ USER’S MANUAL 13.7 PORT 0 AND PORT 2 STATUS This section summarizes the status of the port 0 and port 2 pins when these ports are used as the external bus. A more comprehensive description of the ports and their use is given in Chapter 7, “Input/Output Ports.”...
Page 225: Port 0 And Port 2 Pin Status In
EXTERNAL MEMORY INTERFACE 13.7.2 Port 0 and Port 2 Pin Status in Page Mode In a page-mode bus cycle, the data is multiplexed with the upper address byte on port 2. However, if the instruction uses an 8-bit address (e.g., MOVX @Ri), the contents of P2 are driven onto the pins when data is not on the pins.
Page 226: External Memory Design Examples
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8 EXTERNAL MEMORY DESIGN EXAMPLES This section presents several external memory designs for 8XC251Sx systems. These examples illustrate the design flexibility provided by the configuration options, especially for the PSEN# and RD# signals. Many designs are possible. The examples employ the 8XC251SB but also apply to SA, SP, and SQ devices if the differences in on-chip memory are allowed for.
Page 227 EXTERNAL MEMORY INTERFACE Address Space (256 Kbytes) FFFFH 0000H 128 Kbytes External Flash 128 Kbytes –1056 Bytes External RAM FFFFH 0420H 1056 Bytes On-chip RAM 00:0000H A4220-02 Figure 13-18. Address Space for Example 1 13-19...
Page 228: Example 2: Rd1:0 = 01, 17-Bit Bus, External Flash And Ram
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External Flash and RAM In this example, an 80C251SB operates in page mode with a 17-bit external address bus inter- faced to 64 Kbytes of flash memory for code storage and 32 Kbytes of external RAM (Figure 13-19).
Page 229 EXTERNAL MEMORY INTERFACE Address Space (256 Kbytes) FFFFH 64 Kbytes External Flash 0000H 32 Kbytes –1056 Bytes External RAM 7FFFH 0420H 1056 Bytes On-chip RAM 00:0000H A4168-03 Figure 13-20. Address Space for Example 2 13-21...
Page 230: Example 3: Rd1:0 = 01, 17-Bit Bus, External Ram
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External RAM In this example, an 87C251SB/83C251SB operates in nonpage mode with a 17-bit external ad- dress bus interfaced to 128 Kbytes of external RAM (Figure 13-21). The 87C251SB/83C251SB is configured so that RD# functions as A16, and PSEN# is asserted for all reads.
Page 231 EXTERNAL MEMORY INTERFACE Address Space (256 Kbytes) FFFFH 3FFFH 16 Kbytes On-chip Code Memory 0000H 128 Kbytes –1056 Bytes External RAM FFFFH 0420H 1056 Bytes On-chip RAM 00:0000H A4169-03 Figure 13-22. Address Space for Example 3 13-23...
Page 232: Example 4: Rd1:0 = 10, 16-Bit Bus, External Ram
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External RAM In this example, an 87C251SB/83C251SB operates in nonpage mode with a 16-bit external ad- dress bus interfaced to 64 Kbytes of RAM (Figure 13-23). This configuration leaves P3.7/RD#/A16 available for general I/O (RD1:0 = 10).
Page 233 EXTERNAL MEMORY INTERFACE Address Space (256 Kbytes) FFFFH 3FFFH 16 Kbytes On-chip Code Memory 0000H FFFFH External RAM 64 Kbytes – 1056 Bytes 0420H 1056 Bytes On-chip RAM 00:0000H A4224-02 Figure 13-24. Address Space for Example 4 13-25...
Page 234: Example 5: Rd1:0 = 11, 16-Bit Bus, External Eprom And Ram
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External EPROM and RAM In this example, an 80C251SB operates in nonpage mode with a 16-bit external address bus in- terfaced to 64 Kbytes of EPROM and 64 Kbytes of RAM (Figure 13-25). The 80C251SB is con- figured so that RD# is asserted for addresses ≤...
Page 235 EXTERNAL MEMORY INTERFACE EPROM 80C251SB (64 Kbytes) (64 Kbytes) A15:8 A15:8 A15:8 Code Data A7:0 A/D7:0 Latch A7:0 A7:0 D7:0 D7:0 PSEN# A4145-01 Figure 13-25. Bus Diagram for Example 5: 80C251SB in Nonpage Mode 13-27...
Page 236 8XC251SA, SB, SP, SQ USER’S MANUAL Address Space Address Space (256 Kbytes) (256 Kbytes) 64 Kbytes 64 Kbytes FFFFH FFFFH External EPROM External EPROM 0000H 0000H FFFFH 64 Kbytes External 0000H External RAM FFFFH 64 Kbytes – 1056 Bytes 0420H...
Page 237: Example 6: Rd1:0 = 11, 16-Bit Bus, External Eprom And Ram
EXTERNAL MEMORY INTERFACE 13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External EPROM and RAM In this example, an 80C251SB operates in page mode with a 16-bit external address bus inter- faced to 64 Kbytes of EPROM and 64 Kbytes of RAM (Figure 13-27). The 80C251SB is config- ured so that RD# is asserted for addresses ≤...
Page 238: Example 7: Rd1:0 = 01, 17-Bit Bus, External Flash
8XC251SA, SB, SP, SQ USER’S MANUAL 13.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External Flash In this example, an 80C251SB operates in page mode with a 17-bit external address bus inter- faced to 128 Kbytes of flash memory (Figure 13-28). Port 2 carries both the upper address bits (A15:0) and the data (D7:0), while port 0 carries only the lower address bits (A7:0).
Page 239 Programming and Verifying Nonvolatile Memory...
Page 241: Programming And Verifying
CHAPTER 14 PROGRAMMING AND VERIFYING NONVOLATILE MEMORY This chapter provides instructions for programming and verifying on-chip nonvolatile memory on the 8XC251Sx. The programming instructions cover the entry of program code into on-chip code memory, configuration information into the on-chip configuration bytes, and other catego- ries of information into on-chip memory outside the memory address space.
Page 242: Programming Considerations For On-Chip Code Memory
8XC251SA, SB, SP, SQ USER’S MANUAL In some microcontroller applications, it is desirable that user program code be secure from unau- thorized access. The 8XC251Sx offers two types of protection for program code stored in the on- chip array. •...
Page 243: Eprom Devices
5 V. Verification is performed in a similar manner but without increasing V and without pulsing PROG#. Figure 14-2 shows the program and verify bus cycle waveforms. For waveform timing information, refer to the 8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller Datasheet.
Page 244 8XC251SA, SB, SP, SQ USER’S MANUAL Table 14-1. Programming and Verifying Modes Mode PSEN# PROG# Port Port Address Notes Port 1 (high) Port 3 (low) Program Mode. On-chip High 5 V, 5 Pulses data 1, 4 Code Memory 12.75 V...
Page 245: Programming Algorithm
PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 8XC251S x A0 - A7 Address (16 Bits) Data (8 Bits) A8 - A15 EA#/V Programming Signals XTAL1 ALE/PROG# 4 MHz PSEN# 6 MHz XTAL2 Program/Verify Mode (8 Bits) A4122-02 Figure 14-1. Setup for Programming and Verifying Nonvolatile Memory 14.4 PROGRAMMING ALGORITHM The procedure for programming the 87C251Sx is as follows: Set up the controller for operation in the appropriate mode according to Table 14-1.
Page 246: Verify Algorithm
8XC251SA, SB, SP, SQ USER’S MANUAL Programming Cycle Verification Cycle P1, P3 Address (16-Bit) Address Data In (8-Bit) Data Out PROG# 12.75V EA#/V Mode (8-Bit) Mode A4129-01 Figure 14-2. Program/Verify Bus Cycles 14.5 VERIFY ALGORITHM Use this procedure to verify user program code, signature bytes, configuration bytes, and lock bits stored in nonvolatile memory on the 8XC251Sx.
Page 247: On-Chip Code Memory
PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14.6.1 On-chip Code Memory On-chip code memory is located in the top region of the memory space starting at address FF:0000H. At reset, the 87C251Sx and 83C251Sx devices vector to this address. See Chapter 3, “Address Spaces,”...
Page 248: Encryption Array
8XC251SA, SB, SP, SQ USER’S MANUAL Table 14-2. Lock Bit Function Lock Bits Programmed Protection Type Level 1 No program lock features are enabled. On-chip user code is encrypted when verified, if encryption array is programmed. Level 2 External code is prevented from fetching code bytes from on- chip code memory.
Page 249: Verifying The 83C251Sa, Sb, Sp, Sq (Rom)
Indicates 87C251SB device Indicates 87C251SP device Indicates 87C251SQ device Indicates 8XC251SA, SB, SP, SQ 14.7 VERIFYING THE 83C251SA, SB, SP, SQ (ROM) Nonvolatile memory on the 83C251Sx controller is factory-programmed. The verification proce- dure for the 83C251Sx is exactly the same as for the 87C251Sx. The setup shown in Figure 14-1 applies, as do the waveform and timing diagrams.
Page 251: Instruction Set Reference
Instruction Set Reference...
Page 253 APPENDIX A INSTRUCTION SET REFERENCE ® This appendix contains reference material for the instructions in the MCS 251 architecture. It includes an opcode map, a summary of the instructions — with instruction lengths and execution times — and a detailed description of each instruction. It contains the following tables: •...
Page 254 8XC251SA, SB, SP, SQ USER’S MANUAL NOTATION FOR INSTRUCTION OPERANDS Table A-1. Notation for Register Operands ® MCS 51 Register Notation Arch. Arch. A memory location (00H–FFH) addressed indirectly via byte register R0 or R1 Byte register R0–R7 of the currently selected register bank Byte register index: n = 0–7...
Page 255 INSTRUCTION SET REFERENCE Table A-2. Notation for Direct Addresses ® Direct MCS 51 Description Address. Arch. Arch. dir8 An 8-bit direct address. This can be a memory address (00:0000H–00:00FFH) or an SFR address (S:00H - S:FFH). dir16 A 16-bit memory address (00:0000H–00:FFFFH) used in direct addressing.
Page 256 8XC251SA, SB, SP, SQ USER’S MANUAL OPCODE MAP AND SUPPORTING TABLES ® Table A-6. Instructions for MCS 51 Microcontrollers Bin. A5 x 6–A5 x 7 A5 x 8–A5 x F Src. AJMP LJMP addr11 addr16 dir8 ACALL LCALL bit,rel addr11...
Page 257 INSTRUCTION SET REFERENCE ® Table A-7. New Instructions for the MCS 251 Architecture Bin. A5 x 8 A5 x 9 A5 x A A5 x B A5 x C A5 x D A5 x E A5 x F Src. JSLE MOVZ INC R,#short (1) Rm,@WRj+dis...
Page 258 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-8. Data Instructions Instruction Byte 0 Byte 1 Byte 2 Byte 3 Oper Rmd,Rms Oper WRjd,WRjs jd/2 js/2 Oper DRkd,DRks kd/4 ks/4 Oper Rm,#data 0000 #data Oper WRj,#data16 0100 #data (high) #data (low)
Page 259 INSTRUCTION SET REFERENCE All of the bit instructions in the MCS 251 architecture (Table A-7) have opcode A9, which serves as an escape byte (similar to A5). The high nibble of byte 1 specifies the bit instruction, as given in Table A-10. Table A-10.
Page 260 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-12. PUSH/POP Instructions Instruction Byte 0(x) Byte 1 Byte 2 Byte 3 PUSH #data 0000 0010 #data PUSH #data16 0000 0110 #data16 (high) #data16 (low) PUSH Rm 1000 PUSH WRj 1001 PUSH DRk...
Page 261 INSTRUCTION SET REFERENCE Table A-14. Displacement/Extended MOVs Instruction Byte 0 Byte 1 Byte 2 Byte 3 MOV Rm,@WRj+dis dis[15:8] dis[7:0] MOV WRk,@WRj+dis dis[15:8] dis[7:0] MOV Rm,@DRk+dis dis[15:8] dis[7:0] MOV WRj,@DRk+dis dis[15:8] dis[7:0] MOV @WRj+dis,Rm dis[15:8] dis[7:0] MOV @WRj+dis,WRk dis[15:8] dis[7:0] MOV @DRk+dis,Rm dis[15:8] dis[7:0]...
Page 262 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-15. INC/DEC Instruction Byte 0 Byte 1 INC Rm,#short 00 ss INC WRj,#short j/2 01 ss INC DRk,#short DEC Rm,#short 00 ss DEC WRj,#short 01 ss DEC DRk,#short Table A-16. Encoding for INC/DEC #short Table A-17.
Page 263: Instruction Set Summary
INSTRUCTION SET REFERENCE INSTRUCTION SET SUMMARY This section summarizes the MCS 251 architecture instruction set. Tables A-19 through A-27 list the instructions by category, providing for each instruction a short description, its length in bytes, and its execution time in states. NOTE The instruction execution times given in the tables are for code executing from on-chip code memory and for data that is read from and written to on-chip...
Page 264 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-18. State Times to Access the Port SFRs Case 0 Additional State Times Execution Times Instruction Binary Source Case 1 Case 2 Case 3 Case 4 ADD A,dir8 ADD Rm,dir8 ADDC A,dir8 ANL A,dir8...
Page 265 INSTRUCTION SET REFERENCE Table A-18. State Times to Access the Port SFRs (Continued) Case 0 Additional State Times Execution Times Instruction Binary Source Case 1 Case 2 Case 3 Case 4 ORL CY,/bit51 ORL dir8,#data ORL dir8,A ORL Rm,dir8 SETB bit SETB bit51 SUB Rm,dir8 SUBB A,dir8...
Page 266 8XC251SA, SB, SP, SQ USER’S MANUAL A.3.2 Instruction Summaries Table A-19. Summary of Add and Subtract Instructions dest opnd ← dest opnd + src opnd ADD <dest>,<src> dest opnd ← dest opnd - src opnd Subtract SUB <dest>,<src> (A) ← (A) + src opnd + carry bit Add with Carry ADDC <dest>,<src>...
Page 267 INSTRUCTION SET REFERENCE Table A-20. Summary of Compare Instructions Compare CMP <dest>,<src> dest opnd – src opnd Binary Mode Source Mode Mnemonic <dest>,<src> Notes Bytes States Bytes States Rmd,Rms Reg with reg WRjd,WRjs Word reg with word reg DRkd,DRks Dword reg with dword reg Rm,#data Reg with immediate data WRj,#data16...
Page 268 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-21. Summary of Increment and Decrement Instructions (DPTR) ← (DPTR) + 1 Increment INC DPTR byte ← byte + 1 Increment INC byte dest opnd ← dest opnd + src opnd Increment INC <dest>,<src>...
Page 269 INSTRUCTION SET REFERENCE Table A-23. Summary of Logical Instructions dest opnd ←dest opnd Λ src opnd Logical AND ANL <dest>,<src> dest opnd ← dest opnd V src opnd Logical OR ORL <dest>,<src> dest opnd ← dest opnd ∀ src opnd Logical Exclusive OR XRL <dest>,<src>...
Page 270 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-23. Summary of Logical Instructions (Continued) dest opnd ←dest opnd Λ src opnd Logical AND ANL <dest>,<src> dest opnd ← dest opnd V src opnd Logical OR ORL <dest>,<src> dest opnd ← dest opnd ∀ src opnd Logical Exclusive OR XRL <dest>,<src>...
Page 271 INSTRUCTION SET REFERENCE Table A-24. Summary of Move Instructions destination ← src opnd Move (2) MOV <dest>,<src> destination ← src opnd with sign extend Move with Sign Extension MOVS <dest>,<src> destination ← src opnd with zero extend Move with Zero Extension MOVZ <dest>,<src>...
Page 272 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-24. Summary of Move Instructions (Continued) destination ← src opnd Move (2) MOV <dest>,<src> destination ← src opnd with sign extend Move with Sign Extension MOVS <dest>,<src> destination ← src opnd with zero extend Move with Zero Extension MOVZ <dest>,<src>...
Page 273 INSTRUCTION SET REFERENCE Table A-24. Summary of Move Instructions (Continued) destination ← src opnd Move (2) MOV <dest>,<src> destination ← src opnd with sign extend Move with Sign Extension MOVS <dest>,<src> destination ← src opnd with zero extend Move with Zero Extension MOVZ <dest>,<src>...
Page 274 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-25. Summary of Exchange, Push, and Pop Instructions A ↔ src opnd Exchange Contents XCH <dest>,<src> A3:0 ↔ on-chip RAM bits 3:0 Exchange Digit XCHD <dest>,<src> SP ← SP + 1; (SP) ← src Push PUSH <src>...
Page 275 INSTRUCTION SET REFERENCE Table A-26. Summary of Bit Instructions bit ← 0 Clear Bit CLR bit bit ← 1 Set Bit SETB bit Complement Bit CPL bit bit← Øbit CY ← CY Λ bit AND Carry with Bit ANL CY,bit CY ←...
Page 276 8XC251SA, SB, SP, SQ USER’S MANUAL Table A-27. Summary of Control Instructions Binary Mode Source Mode Mnemonic <dest>,<src> Notes Bytes States (2) Bytes States (2) ACALL addr11 Absolute subroutine call @DRk Extended subroutine call, indirect ECALL addr24 Extended subroutine call...
Page 277 INSTRUCTION SET REFERENCE Table A-27. Summary of Control Instructions (Continued) Binary Mode Source Mode Mnemonic <dest>,<src> Notes Bytes States (2) Bytes States (2) JSLE Jump if less than or equal (signed) Jump if greater than (signed) JSGE Jump if greater than or equal (signed) A,dir8,rel Compare dir byte to acc and jump...
Page 278 8XC251SA, SB, SP, SQ USER’S MANUAL INSTRUCTION DESCRIPTIONS This section describes each instruction in the MCS 251 architecture. See the note on page A-11 regarding execution times. Table A-28 defines the symbols ( , , 1, 0,?) used to indicate the effect of the instruction on the —...
Page 279 INSTRUCTION SET REFERENCE [Encoding] a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: ACALL (PC) ← (PC) + 2 (SP) ← (SP) + 1 ((SP)) ←...
Page 280 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (A) ← (A) + #data ADD A,dir8 Binary Mode Source Mode Bytes: States: 1† 1† †If this instruction addresses a port (P x , x = 0–3), add 1 state.
Page 281 INSTRUCTION SET REFERENCE [Encoding] 0 0 1 0 1 1 0 0 s s s s S S S S Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rmd) ← (Rmd) + (Rms) ADD WRjd,WRjs Binary Mode Source Mode Bytes: States:...
Page 282 8XC251SA, SB, SP, SQ USER’S MANUAL ADD WRj,#data16 Binary Mode Source Mode Bytes: States: [Encoding] 0 0 1 0 1 1 1 0 t t t t 0 1 0 0 #data hi #data low Hex Code in: Binary Mode = [A5][Encoding]...
Page 283 INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding Operation: (WRj) ← (WRj) + (dir8) ADD Rm,dir16 Binary Mode Source Mode Bytes: States: [Encoding] 0 0 1 0 1 1 1 0 s s s s 0 0 1 1 direct addr direct add...
Page 284 8XC251SA, SB, SP, SQ USER’S MANUAL ADD Rm,@DRk Binary Mode Source Mode Bytes: States: [Encoding] 0 0 1 0 1 1 1 0 u u u u 1 0 1 1 s s s s 0 0 0 0 Hex Code in:...
Page 285 INSTRUCTION SET REFERENCE [Encoding] 0 0 1 1 0 1 0 0 immed. data Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: ADDC (A) ← (A) + (CY) + #data ADDC A,dir8 Binary Mode Source Mode Bytes: States: 1†...
Page 286 8XC251SA, SB, SP, SQ USER’S MANUAL AJMP addr11 Function: Absolute jump Description: Transfers program execution to the specified address, which is formed at run time by concatenating the upper five bits of the PC (after incrementing the PC twice), opcode bits 7–...
Page 287 INSTRUCTION SET REFERENCE Example: Register 1 contains 0C3H (11000011B) and register 0 contains 55H (01010101B). After executing the instruction ANL R1,R0 register 1 contains 41H (01000001B). When the destination is a directly addressed byte, this instruction clears combinations of bits in any RAM location or hardware register.
Page 288 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (A) ← (A) Λ #data ANL A,dir8 Binary Mode Source Mode Bytes: States: 1† 1† †If this instruction addresses a port (P x , x = 0–3), add 1 state.
Page 289 INSTRUCTION SET REFERENCE [Encoding] 0 1 0 1 1 1 0 0 s s s s S S S S Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rmd) ← (Rmd) Λ (Rms) ANL WRjd,WRjs Binary Mode Source Mode Bytes: States:...
Page 290 8XC251SA, SB, SP, SQ USER’S MANUAL ANL Rm,dir8 Binary Mode Source Mode Bytes: States: 3† 2† †If this instruction addresses a port (P x , x = 0–3), add 1 state. [Encoding] 0 1 0 1 1 1 1 0...
Page 291 INSTRUCTION SET REFERENCE [Encoding] 0 1 0 1 1 1 1 0 t t t t 0 1 1 1 direct direct Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) ← (WRj) Λ (dir16) ANL Rm,@WRj Binary Mode Source Mode Bytes:...
Page 292 8XC251SA, SB, SP, SQ USER’S MANUAL Flags: — — — — Example: Set the CY flag if, and only if, P1.0 = 1, ACC. 7 = 1, and OV = 0: MOV CY,P1.0 ;Load carry with input pin state ANL CY,ACC.7 ;AND carry with accumulator bit 7 ANL CY,/OV ;AND with inverse of overflow flag...
Page 293 INSTRUCTION SET REFERENCE Operation: (CY) ← (CY) Λ (bit) ANL CY,/bit Binary Mode Source Mode Bytes: States: 3† 2† †If this instruction addresses a port (P x , x = 0–3), add 1 state. [Encoding] 1 0 1 0 1 0 0 1 1 1 1 1 y y y dir addr...
Page 294 8XC251SA, SB, SP, SQ USER’S MANUAL Variations CJNE A,#data,rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: States: [Encoding] 1 0 1 1 0 1 0 0 immed. data rel. addr Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] (PC) ←...
Page 295 INSTRUCTION SET REFERENCE [Encoding] 1 0 1 1 0 1 1 i immed. data rel. addr Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] (PC) ← (PC) + 3 Operation: IF ((Ri)) ≠ #data THEN (PC) ← (PC) + relative offset IF ((Ri)) <...
Page 296 8XC251SA, SB, SP, SQ USER’S MANUAL Binary Mode Source Mode Bytes: States: [Encoding] 1 1 1 0 0 1 0 0 Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (A) ← 0 CLR bit Function: Clear bit Description: Clears the specified bit.
Page 297 INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (CY) ← 0 CLR bit Binary Mode Source Mode Bytes: States: 4† 3† †If this instruction addresses a port (P x , x = 0–3), add 2 states. [Encoding] 1 0 1 0 1 0 0 1...
Page 298 8XC251SA, SB, SP, SQ USER’S MANUAL [Encoding] 1 0 1 1 1 1 0 0 s s s s S S S S Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rmd) – (Rms) CMP WRjd,WRjs...
Page 299 INSTRUCTION SET REFERENCE CMP WRj,#data16 Binary Mode Source Mode Bytes: States: [Encoding] 1 0 1 1 1 1 1 0 t t t t 0 1 0 0 #data hi #data low Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) –...
Page 300 8XC251SA, SB, SP, SQ USER’S MANUAL [Encoding] 1 0 1 1 1 1 1 0 s s s s 0001 dir addr Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rm) – (dir8) CMP WRj,dir8 Binary Mode...
Page 301 INSTRUCTION SET REFERENCE CMP Rm,@WRj Binary Mode Source Mode Bytes: States: [Encoding] 1 0 1 1 1 1 1 0 t t t t 1 0 0 1 s s s s 0 0 0 0 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rm) –...
Page 302 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (A) ← Ø(A) CPL bit Function: Complement bit Description: Complements (Ø) the specified bit variable. A clear bit is set, and a set bit is cleared. CPL can operate on the CY or any directly addressable bit.
Page 303 INSTRUCTION SET REFERENCE Operation: (CY) ← Ø(CY) CPL bit Binary Mode Source Mode Bytes: States: 4† 3† †If this instruction addresses a port (P x , x = 0–3), add 2 states. [Encoding] 1 0 1 0 1 0 0 1 1 0 1 1 y y y dir addr...
Page 304 8XC251SA, SB, SP, SQ USER’S MANUAL Example: The accumulator contains 56H (01010110B), which represents the packed BCD digits of the decimal number 56. Register 3 contains 67H (01100111B), which represents the packed BCD digits of the decimal number 67. The CY flag is set. After executing the instruction...
Page 305 INSTRUCTION SET REFERENCE Example: Register 0 contains 7FH (01111111B). On-chip RAM locations 7EH and 7FH contain 00H and 40H, respectively. After executing the instruction sequence DEC @R0 DEC R0 DEC @R0 register 0 contains 7EH and on-chip RAM locations 7EH and 7FH are set to 0FFH and 3FH, respectively.
Page 306 8XC251SA, SB, SP, SQ USER’S MANUAL DEC Rn Binary Mode Source Mode Bytes: States: [Encoding] 0 0 0 1 1 r r r Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: (Rn) ← (Rn) – 1 DEC <dest>,<src>...
Page 307 INSTRUCTION SET REFERENCE [Encoding] 0 0 0 1 1 0 1 1 t t t t Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) ← (WRj) – #short DEC DRk,#short Binary Mode Source Mode Bytes: States: [Encoding] 0 0 0 1...
Page 308 8XC251SA, SB, SP, SQ USER’S MANUAL Variations DIV Rmd Rms Binary Mode Source Mode Bytes: States: [Encoding] 1 0 0 0 1 1 0 0 s s s s S S S S Hex Code in: Binary Mode = [A5][Encoding]...
Page 309 INSTRUCTION SET REFERENCE Exception: if register B contains 00H, the values returned in the accumulator and register B are undefined; the CY flag is cleared and the OV flag is set. Flags: — For division by zero: — Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Example:...
Page 310 8XC251SA, SB, SP, SQ USER’S MANUAL Example: The on-chip RAM locations 40H, 50H, and 60H contain 01H, 70H, and 15H, respectively. After executing the following instruction sequence DJNZ 40H,LABEL1 DJNZ 50H,LABEL2 DJNZ 60H,LABEL on-chip RAM locations 40H, 50H, and 60H contain 00H, 6FH, and 14H, respectively, and program execution continues at label LABEL2.
Page 311 INSTRUCTION SET REFERENCE Operation: DJNZ (PC) ← (PC) + 2 (Rn) ← (Rn) – 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) ← (PC) + rel ECALL <dest> Function: Extended call Description: Calls a subroutine located at the specified address. The instruction adds four to the program counter to generate the address of the next instruction and then pushes the 24-bit result onto the stack (high byte first), incrementing the stack pointer by three.
Page 312 8XC251SA, SB, SP, SQ USER’S MANUAL ECALL @DRk Binary Mode Source Mode Bytes: States: [Encoding] 1 0 0 1 1 0 0 1 u u u u Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ECALL (PC) ←...
Page 313 INSTRUCTION SET REFERENCE EJMP @DRk Binary Mode Source Mode Bytes: States: [Encoding] 1 0 0 0 1 0 0 1 u u u u Hex Code in: Binary Mode = [A5] [Encoding] Source Mode = [Encoding] Operation: EJMP (PC) ← ((DRk)) ERET Function: Extended return...
Page 314 8XC251SA, SB, SP, SQ USER’S MANUAL Flags: — — — Example: Register 0 contains 7EH (011111110B) and on-chip RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. After executing the instruction sequence INC @R0 INC R0 INC @R0 register 0 contains 7FH and on-chip RAM locations 7EH and 7FH contain 00H and 41H, respectively.
Page 315 INSTRUCTION SET REFERENCE Operation: ((Ri) ← ((Ri)) + 1 INC Rn Binary Mode Source Mode Bytes: States: [Encoding] 0 0 0 0 1 r r r Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: (Rn) ← (Rn) + 1 INC <dest>,<src>...
Page 316 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) ← (WRj) + #short INC DRk,#short Binary Mode Source Mode Bytes: States: [Encoding] 0 0 0 0 1 0 1 1...
Page 317 INSTRUCTION SET REFERENCE JB bit51,rel JB bit,rel Function: Jump if bit set Description: If the specified bit is a one, jump to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
Page 318 8XC251SA, SB, SP, SQ USER’S MANUAL Operation: (PC) ← (PC) + 3 IF (bit) = 1 THEN (PC) ← (PC) + rel JBC bit51,rel JBC bit,rel Function: Jump if bit is set and clear bit Description: If the specified bit is one, branch to the specified address; otherwise proceed with the next instruction.
Page 319 INSTRUCTION SET REFERENCE JBC bit,rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: States: [Encoding] 1 0 1 0 1 0 0 1 0 0 0 1 y y y direct addr rel. addr Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation:...
Page 320 8XC251SA, SB, SP, SQ USER’S MANUAL Operation: (PC) ← (PC) + 2 IF (CY) = 1 THEN (PC) ← (PC) + rel JE rel Function: Jump if equal Description: If the Z flag is set, branch to the address specified; otherwise proceed with the next instruction.
Page 321 INSTRUCTION SET REFERENCE Example: The instruction JG LABEL1 causes program execution to continue at label LABEL1 if the Z flag and the CY flag are both clear. Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: States: [Encoding] 0 0 1 1 1 0 0 0 rel.
Page 322 8XC251SA, SB, SP, SQ USER’S MANUAL Operation: (PC) ← (PC) + 2 IF (Z) = 1 OR (CY) = 1 THEN (PC) ← (PC) + rel JMP @A+DPTR Function: Jump indirect Description: Add the 8-bit unsigned contents of the accumulator with the 16-bit data pointer and load the resulting sum into the lower 16 bits of the program counter.
Page 323 INSTRUCTION SET REFERENCE Flags: — — — — — Example: Input port 1 contains 11001010B and the accumulator contains 56H (01010110B). After executing the instruction sequence JNB P1.3,LABEL1 JNB ACC.3,LABEL2 program execution continues at label LABEL2. Variations JNB bit51,rel Binary Mode Source Mode Not Taken Taken...
Page 324 8XC251SA, SB, SP, SQ USER’S MANUAL JNC rel Function: Jump if carry not set Description: If the CY flag is clear, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction.
Page 325 INSTRUCTION SET REFERENCE Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: States: [Encoding] 0 1 1 1 1 0 0 0 rel. addr Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (PC) ← (PC) + 2 IF (Z) = 0 THEN (PC) ←...
Page 326 8XC251SA, SB, SP, SQ USER’S MANUAL JSG rel Function: Jump if greater than (signed) Description: If the Z flag is clear AND the N flag and the OV flag have the same value, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
Page 327 INSTRUCTION SET REFERENCE Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: States: [Encoding] 0 1 0 1 1 0 0 0 rel. addr Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: JSGE (PC) ← (PC) + 2 IF [(N) = (OV)] THEN (PC) ←...
Page 328 8XC251SA, SB, SP, SQ USER’S MANUAL JSLE rel Function: Jump if less than or equal (signed) Description: If the Z flag is set OR if the the N flag and the OV flag have different values, branch to the address specified; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC, after incrementing the PC twice.
Page 329 INSTRUCTION SET REFERENCE Example: The accumulator contains 01H. After executing the instruction sequence JZ LABEL1 DEC A JZ LABEL2 the accumulator contains 00H and program execution continues at label LABEL2. Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes: States: [Encoding]...
Page 330 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: LCALL (PC) ← (PC) + 3 (SP) ← (SP) + 1 ((SP)) ← (PC.7:0) (SP) ← (SP) + 1 ((SP)) ← (PC.15:8) (PC) ←...
Page 331 INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: LJMP (PC) ← (addr.15:0) LJMP @WRj Binary Mode Source Mode Bytes: States: [Encoding] 1 0 0 0 1 0 0 1 t t t t 0 1 0 0 Hex Code in: Binary Mode = [A5] [Encoding]...
Page 332 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (A) ← #data MOV dir8,#data Binary Mode Source Mode Bytes: States: 3† 3† †If this instruction addresses a port (P x , x = 0–3), add 1 state.
Page 333 INSTRUCTION SET REFERENCE [Encoding] 1 0 0 0 0 1 0 1 direct addr direct addr Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (dir8) ← (dir8) MOV dir8,@Ri Binary Mode Source Mode Bytes: States: [Encoding] 1 0 0 0 0 1 1 i direct addr...
Page 334 8XC251SA, SB, SP, SQ USER’S MANUAL MOV Rn,dir8 Binary Mode Source Mode Bytes: States: 1† 2† †If this instruction addresses a port (P x , x = 0–3), add 1 state. [Encoding] 1 0 1 0 1 r r r...
Page 335 INSTRUCTION SET REFERENCE Operation: (A) ← (Rn) MOV dir8,A Binary Mode Source Mode Bytes: States: 2† 2† †If this instruction addresses a port (P x , x = 0–3), add 1 state. [Encoding] 1 1 1 1 0 1 0 1 direct addr Hex Code in: Binary Mode = [Encoding]...
Page 336 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rmd) ← (Rms) MOV WRjd,WRjs Binary Mode Source Mode Bytes: States: [Encoding] 0 1 1 1 1 1 0 1 t t t t...
Page 337 INSTRUCTION SET REFERENCE [Encoding] 0 1 1 1 1 1 1 0 t t t t 0 1 0 0 #data hi #data low Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) ← #data16 MOV DRk,#0data16 Binary Mode Source Mode Bytes:...
Page 338 8XC251SA, SB, SP, SQ USER’S MANUAL Operation: (Rm) ← (dir8) MOV WRj,dir8 Binary Mode Source Mode Bytes: States: [Encoding] 0 1 1 1 1 1 1 0 t t t t 0 1 0 1 direct addr Hex Code in:...
Page 339 INSTRUCTION SET REFERENCE [Encoding] 0 1 1 1 1 1 1 0 t t t t 0 1 1 1 direct addr direct addr Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) ← (dir16) MOV DRk,dir16 Binary Mode Source Mode Bytes:...
Page 340 8XC251SA, SB, SP, SQ USER’S MANUAL MOV WRjd,@WRjs Binary Mode Source Mode Bytes: States: [Encoding] 0 0 0 0 1 0 1 1 T T T T 1 0 0 0 t t t t 0 0 0 0 Hex Code in:...
Page 341 INSTRUCTION SET REFERENCE [Encoding] 0 1 1 1 1 0 1 0 t t t t 0 1 0 1 direct addr Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (dir8) ← (WRj) MOV dir8,DRk Binary Mode Source Mode Bytes: States:...
Page 342 8XC251SA, SB, SP, SQ USER’S MANUAL MOV dir16,DRk Binary Mode Source Mode Bytes: States: [Encoding] 0 1 1 1 1 0 1 0 u u u u 1 1 1 1 direct addr direct addr Hex Code in: Binary Mode = [A5][Encoding]...
Page 343 INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ((WRjd)) ← (WRjs) MOV @DRk,WRj Binary Mode Source Mode Bytes: States: [Encoding] 0 0 0 1 1 0 1 1 u u u u 1 0 1 0 t t t t 0 0 0 0 Hex Code in:...
Page 344 8XC251SA, SB, SP, SQ USER’S MANUAL MOV Rm,@DRk + dis24 Binary Mode Source Mode Bytes: States: [Encoding] 0 0 1 0 1 0 0 1 s s s s u u u u dis hi dis low Hex Code in:...
Page 345 INSTRUCTION SET REFERENCE [Encoding] 0 1 0 1 1 0 0 1 t t t t T T T T dis hi dis low Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: ((WRj)) + (dis) ← (WRj) MOV @DRk + dis24,Rm Binary Mode Source Mode...
Page 346 8XC251SA, SB, SP, SQ USER’S MANUAL Example: The CY flag is set, input Port 3 contains 11000101B, and output Port 1 contains 35H (00110101B). After executing the instruction sequence MOV P1.3,CY MOV CY,P3.3 MOV P1.2,CY the CY flag is clear and Port 1 contains 39H (00111001B).
Page 347 INSTRUCTION SET REFERENCE Operation: (bit) ← (CY) MOV CY,bit Binary Mode Source Mode Bytes: States: 3† 2† †If this instruction addresses a port (P x , x = 0–3), add 1 state. [Encoding] 1 0 1 0 1 0 0 1 1 0 1 0 y y y direct addr...
Page 348 8XC251SA, SB, SP, SQ USER’S MANUAL MOVC A,@A+<base–reg> Function: Move code byte Description: Loads the accumulator with a code byte or constant from program memory. The address of the byte fetched is the sum of the original unsigned 8-bit accumulator contents and the contents of a 16-bit base register, which may be the 16 LSBs of the data pointer or PC.
Page 349 INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: MOVC (A) ← ((A) + (DPTR)) MOVH DRk,#data16 Function: Move immediate 16-bit data to the high word of a dword (double-word) register Description: Moves 16-bit immediate data to the high word of a dword (32-bit) register. The low word of the dword register is unchanged.
Page 350 8XC251SA, SB, SP, SQ USER’S MANUAL Example: Eight-bit register Rm contains 055H (01010101B) and the 16-bit register WRj contains 0FFFFH (11111111 11111111B). The instruction MOVS WRj,Rm moves the contents of register Rm (01010101B) to register WRj (i.e., WRj contains 00000000 01010101B).
Page 351 The MCS 251 controller is operating in nonpage mode. An external 256-byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/I/O/Timer) is connected to port 0. Port 3 provides control lines for the external RAM. ports 1 and 2 are used for normal I/O. R0 and R1 contain 12H and 34H.
Page 352 8XC251SA, SB, SP, SQ USER’S MANUAL MOVX @Ri,A Binary Mode Source Mode Bytes: States: [Encoding] 1 1 1 1 0 0 1 i Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: MOVX ((Ri)) ← (A) MOVZ WRj,Rm...
Page 353 INSTRUCTION SET REFERENCE MUL <dest>,<src> Function: Multiply Description: Multiplies the unsigned integer in the source register with the unsigned integer in the destination register. Only register addressing is allowed. For 8-bit operands, the result is 16 bits. The most significant byte of the result is stored in the low byte of the word where the destination register resides.
Page 354 8XC251SA, SB, SP, SQ USER’S MANUAL MUL WRjd,WRjs Binary Mode Source Mode Bytes: States: [Encoding] 1 0 1 0 1 1 0 1 t t t t t t t t Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]...
Page 355 INSTRUCTION SET REFERENCE Function: No operation Description: Execution continues at the following instruction. Affects the PC register only. Flags: — — — — — Example: You want to produce a low-going output pulse on bit 7 of Port 2 that lasts exactly 11 states. A simple CLR-SETB sequence generates an eight-state pulse.
Page 356 8XC251SA, SB, SP, SQ USER’S MANUAL Example: The accumulator contains 0C3H (11000011B) and R0 contains 55H (01010101B). After executing the instruction ORL A,R0 the accumulator contains 0D7H (11010111B). When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register.
Page 357 INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (A) ← (A) V #data ORL A,dir8 Binary Mode Source Mode Bytes: States: 1† 1† †If this instruction addresses a port (P x , x = 0–3), add 1 state. [Encoding] 0 1 0 0 0 1 0 1...
Page 358 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rmd) ← (Rmd) V (Rms) ORL WRjd,WRjs Binary Mode Source Mode Bytes: States: [Encoding] 0 1 0 0 1 1 0 1...
Page 359 INSTRUCTION SET REFERENCE ORL Rm,dir8 Binary Mode Source Mode Bytes: States: 3† 2† †If this instruction addresses a port (P x , x = 0–3), add 1 state. [Encoding] 0 1 0 0 1 1 1 0 s s s s 0 0 0 1 direct addr Hex Code in:...
Page 360 8XC251SA, SB, SP, SQ USER’S MANUAL [Encoding] 0 1 0 0 1 1 1 0 t t t t 0 1 1 1 direct addr direct addr Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) ← (WRj) V (dir16)
Page 361 INSTRUCTION SET REFERENCE Example: Set the CY flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0: MOV CY,P1.0 ;LOAD CARRY WITH INPUT PIN P10 ORL CY,ACC.7 ;OR CARRY WITH THE ACC. BIT 7 ORL CY,/OV ;OR CARRY WITH THE INVERSE OF OV.
Page 362 8XC251SA, SB, SP, SQ USER’S MANUAL ORL CY,/bit Binary Mode Source Mode Bytes: States: 3† 2† †If this instruction addresses a port (P x , x = 0–3), add 1 state. [Encoding] 1 0 1 0 1 0 0 1...
Page 363 INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (dir8) ← ((SP)) (SP) ← (SP) – 1 POP Rm Binary Mode Source Mode Bytes: States: [Encoding] 1 1 0 1 1 0 1 0 s s s s 1 0 0 0 Hex Code in:...
Page 364 8XC251SA, SB, SP, SQ USER’S MANUAL PUSH <dest> Function: Push onto stack Description: Increments the stack pointer by one. The contents of the specified variable are then copied into the on-chip RAM location addressed by the stack pointer. Flags: —...
Page 365 INSTRUCTION SET REFERENCE PUSH #data16 Binary Mode Source Mode Bytes: States: [Encoding] 1 1 0 0 1 0 1 0 0 0 0 0 0 1 1 0 #data hi #data lo Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: PUSH (SP) ←...
Page 366 8XC251SA, SB, SP, SQ USER’S MANUAL PUSH DRk Binary Mode Source Mode Bytes: States: [Encoding] 1 1 0 0 1 0 1 0 u u u u 1 0 1 1 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]...
Page 367 INSTRUCTION SET REFERENCE RETI Function: Return from interrupt Description: This instruction pops two or four bytes from the stack, depending on the INTR bit in the CONFIG1 register. If INTR = 0, RETI pops the high and low bytes of the PC successively from the stack and uses them as the 16-bit return address in region FF:.
Page 368 8XC251SA, SB, SP, SQ USER’S MANUAL Operation for INTR = 1: RETI (PC).15:8 ← ((SP)) (SP) ← (SP) – 1 PC).7:0 ← ((SP)) (SP) ← (SP) – 1 (PC).23:16 ← ((SP)) (SP) ← (SP) – 1 PSW1 ← ((SP)) (SP) ← (SP) – 1...
Page 369 INSTRUCTION SET REFERENCE Example: The accumulator contains 0C5H (11000101B) and the CY flag is clear. After executing the instruction RLC A the accumulator contains 8AH (10001010B) and the CY flag is set. Binary Mode Source Mode Bytes: States: [Encoding] 0 0 1 1 0 0 1 1 Hex Code in: Binary Mode = [Encoding]...
Page 370 8XC251SA, SB, SP, SQ USER’S MANUAL RRC A Function: Rotate accumulator right through carry flag Description: Rotates the eight bits in the accumulator and the CY flag one bit to the right. Bit 0 moves into the CY flag position; the original value of the CY flag moves into the bit 7 position.
Page 371 INSTRUCTION SET REFERENCE SETB bit51 Binary Mode Source Mode Bytes: States: 2† 2† †If this instruction addresses a port (P x , x = 0–3), add 2 states. [Encoding] 1 1 0 1 0 0 1 0 bit addr Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation:...
Page 372 8XC251SA, SB, SP, SQ USER’S MANUAL Flags: — — — — — Example: The label "RELADR" is assigned to an instruction at program memory location 0123H. The instruction SJMP RELADR assembles into location 0100H. After executing the instruction, the PC contains 0123H.
Page 373 INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rm).a+1 ← (Rm).a (Rm).0 ← 0 CY ← (Rm).7 SLL WRj Binary Mode Source Mode Bytes: States: [Encoding] 0 0 1 1 1 1 1 0 t t t t 0 1 0 0 Hex Code in:...
Page 374 8XC251SA, SB, SP, SQ USER’S MANUAL SRA WRj Binary Mode Source Mode Bytes: States: [Encoding] 0 0 0 0 1 1 1 0 t t t t 0 1 0 0 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj).15 ←...
Page 375 INSTRUCTION SET REFERENCE SRL WRj Binary Mode Source Mode Bytes: States: [Encoding] 0 0 0 1 1 1 1 0 t t t t 0 1 0 0 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj).15 ←...
Page 376 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rmd) ← (Rmd) – (Rms) SUB WRjd,WRjs Binary Mode Source Mode Bytes: States: [Encoding] 1 0 0 1 1 1 0 1...
Page 377 INSTRUCTION SET REFERENCE [Encoding] 1 0 0 1 1 1 1 0 t t t t 0 1 0 0 #data hi #data low Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) ← (WRj) – #data16 SUB DRk,#data16 Binary Mode Source Mode...
Page 378 8XC251SA, SB, SP, SQ USER’S MANUAL SUB Rm,dir16 Binary Mode Source Mode Bytes: States: [Encoding] 1 0 0 1 1 1 1 0 s s s s 0 0 1 1 direct addr direct addr Hex Code in: Binary Mode = [A5][Encoding]...
Page 379 INSTRUCTION SET REFERENCE [Encoding] 1 0 0 1 1 1 1 0 u u u u 1 0 1 1 s s s s 0 0 0 0 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rm) ←...
Page 380 8XC251SA, SB, SP, SQ USER’S MANUAL [Encoding] 1 0 0 1 0 1 0 0 immed. data Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: SUBB (A) ← (A) – (CY) – #data SUBB A,dir8 Binary Mode...
Page 381 PSW0 and PSW1. Interrupt calls can not occur immediately following this instruction. This instruction is intended for use by Intel-provided development tools. These tools do not support user application of this instruction.
Page 382 8XC251SA, SB, SP, SQ USER’S MANUAL Binary Mode Source Mode Bytes: States (2 bytes): States (4 bytes): [Encoding] 1 0 1 1 1 0 0 1 Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: TRAP SP ← SP – 2 (SP) ←...
Page 383 INSTRUCTION SET REFERENCE XCH A,@Ri Binary Mode Source Mode Bytes: States: [Encoding] 1 1 0 0 0 1 1 i Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: (A) → ← ((Ri)) XCH A,Rn Binary Mode Source Mode Bytes: States:...
Page 384 8XC251SA, SB, SP, SQ USER’S MANUAL Binary Mode Source Mode Bytes: States: [Encoding] 1 1 0 1 0 1 1 i Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: XCHD (A).3:0 → ← ((Ri)).3:0 XRL <dest>,<src>...
Page 385 INSTRUCTION SET REFERENCE [Encoding] 0 1 1 0 0 0 1 0 direct addr Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding] Operation: (dir8) ← (dir8) ∀ (A) XRL dir8,#data Binary Mode Source Mode Bytes: States: 3† 3†...
Page 386 8XC251SA, SB, SP, SQ USER’S MANUAL XRL A,@Ri Binary Mode Source Mode Bytes: States: [Encoding] 0 1 1 0 0 1 1 i Hex Code in: Binary Mode = [Encoding] Source Mode = [A5][Encoding] Operation: (A) ← (A) ∀ ((Ri))
Page 387 INSTRUCTION SET REFERENCE Operation: (WRds) ← (WRjd) ∀ (WRjs) XRL Rm,#data Binary Mode Source Mode Bytes: States: [Encoding] 0 1 1 0 1 1 1 0 s s s s 0 0 0 0 #data Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rm) ←...
Page 388 8XC251SA, SB, SP, SQ USER’S MANUAL Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (WRj) ← (WRj) ∀ (dir8) XRL Rm,dir16 Binary Mode Source Mode Bytes: States: [Encoding] 0 1 1 0 1 1 1 0...
Page 389 INSTRUCTION SET REFERENCE XRL Rm,@Drk Binary Mode Source Mode Bytes: States: [Encoding] 0 1 1 0 1 1 1 0 u u u u 1 0 1 1 s s s s 0 0 0 0 Hex Code In: Binary Mode = [A5][Encoding] Source Mode = [Encoding] Operation: (Rm) ←...
Page 391 Signal Descriptions...
Page 393 P3.2 / INT0# PSEN# View of component as P3.3 / INT1# A15 / P2.7 P3.4 / T0 mounted on PC board A14 / P2.6 P3.5 / T1 A13 / P2.5 A4205-02 Figure B-1. 8XC251SA, SB, SP, SQ 44-pin PLCC Package...
Page 394 8XC251SA, SB, SP, SQ USER’S MANUAL Table B-1. PLCC/DIP Pin Assignments Listed by Functional Category Address & Data Input/Output Name PLCC Name PLCC AD0/P0.0 P1.0/T2 AD1/P0.1 P1.1/T2EX AD2/P0.2 P1.2/ECI AD3/P0.3 P1.3/CEX0 AD4/P0.4 P1.4/CEX1 AD5/P0.5 P1.5/CEX2 AD6/P0.6 P1.6/CEX3/WAIT# AD7/P0.7 P1.7/CEX4/A17WCLK A8/P2.0 P3.0/RXD...
Page 395 P3.7 / RD# / A16 A11 / P2.3 XTAL2 A10 / P2.2 XTAL1 A9 / P2.1 A8 / P2.0 A4206-03 Figure B-2. 8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages Table B-2. Signal Descriptions Signal Alternate Type Description Name Function Address Line A17.
Page 396 8XC251SA, SB, SP, SQ USER’S MANUAL Table B-2. Signal Descriptions (Continued) Signal Alternate Type Description Name Function CEX2:0 Programmable Counter Array (PCA) Input/Output Pins. These P1.5:3 CEX3 P1.6/WAIT# are input signals for the PCA capture mode and output signals for CEX4 P1.7/A17/WCLK...
Page 397 — bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SA, SB, SP, SQ as a pin-for-pin replacement for the 8XC51BH, V can be unconnected without loss of compatibility. (Not available on DIP.) †...
Page 398 8XC251SA, SB, SP, SQ USER’S MANUAL Table B-2. Signal Descriptions (Continued) Signal Alternate Type Description Name Function Secondary Ground 2. This ground is provided to reduce ground — bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, V be unconnected without loss of compatibility.
Page 399 SIGNAL DESCRIPTIONS Table B-3. Memory Signal Selections (RD1:0) P1.7/CEX/ RD1:0 P3.7/RD#/A16/ PSEN# Features A17/WCLK Asserted for Asserted for writes to 256-Kbyte external all addresses all memory locations memory P1.7/CEX4/ Asserted for Asserted for writes to 128-Kbyte external WCLK all addresses all memory locations memory P1.7/CEX4/...
Page 401 Registers...
Page 403 The remainder of the appendix contains descriptions of the SFRs arranged in alphabetical order. For additional information see section 3.3, “8XC251SA, SB, SP, SQ Register File,” and section 3.4, “Special Function Registers (SFRs).”...
Page 404 8XC251SA, SB, SP, SQ USER’S MANUAL Table C-1. 8XC251SA, SB, SP, SQ SFR Map CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000 CCON CMOD...
Page 405 REGISTERS Table C-2. Core SFRs Mnemonic Name Address † Accumulator S:E0H † B Register S:F0H Program Status Word S:D0H PSW1 Program Status Word 1 S:D1H † Stack Pointer – LSB of SPX S:81H † Stack Pointer High – MSB of SPX S:BEH †...
Page 406 8XC251SA, SB, SP, SQ USER’S MANUAL Table C-4. Serial I/O SFRs Mnemonic Name Address SCON Serial Control S:98H SBUF Serial Data Buffer S:99H SADEN Slave Address Mask S:B9H SADDR Slave Address S:A9H Table C-5. Timer/Counter and Watchdog Timer SFRs Mnemonic...
Page 407 REGISTERS Table C-6. Programmable Counter Array (PCA) SFRs Mnemonic Name Address CCON PCA Timer/Counter Control S:D8H CMOD PCA Timer/Counter Mode S:D9H CCAPM0 PCA Timer/Counter Mode 0 S:DAH CCAPM1 PCA Timer/Counter Mode 1 S:DBH CCAPM2 PCA Timer/Counter Mode 2 S:DCH CCAPM3 PCA Timer/Counter Mode 3 S:DDH CCAPM4...
Page 408 8XC251SA, SB, SP, SQ USER’S MANUAL Table C-7. Register File Mnemonic Address R0 – R7 Four banks of 8 registers. Select bank 0-3 with bits 1, 2 RS1:0 of PSW. R8 – R31 R11 = Accumulator (ACC) 1, 3 R10 = B Register.
Page 409 REGISTERS Address: Reset State: 0000 0000B Accumulator. ACC provides SFR access to the accumulator, which resides in the register file as byte ® register R11 (also named ACC). Instructions in the MCS 51 architecture use the accumulator as both source and destination for calculations and moves. Instructions in the MCS 251 architecture assign no special significance to R11.
Page 410 8XC251SA, SB, SP, SQ USER’S MANUAL Address: CCAP0H,L S:FAH, S:EAH CCAPxH, CCAPxL (x = 0–4) CCAP1H,L S:FBH, S:EBH CCAP2H,L S:FCH, S:ECH CCAP3H,L S:FDH, S:EDH CCAP4H,L S:FEH, S:EEH Reset State: XXXX XXXXB PCA Module Compare/Capture Registers. These five register pairs store the 16-bit comparison value or captured value for the corresponding compare/capture modules.
Page 411 REGISTERS Address: CCAPM0 S:DAH CCAPM x ( x = 0–4) CCAPM1 S:DBH CCAPM2 S:DCH CCAPM3 S:DDH CCAPM4 S:DEH Reset State: X000 0000B PCA Compare/Capture Module Mode Registers. These five registers select the operating mode of the corresponding compare/capture module. Each register also contains an enable interrupt bit (ECCFx) for generating an interrupt request when the module’s compare/capture flag (CCF x in the CCON register) is set.
Page 412 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:D8H CCON Reset State: 00X0 0000B PCA Timer/Counter Control Register. Contains the run control bit and overflow flag for the PCA timer/counter, and the compare/capture flags for the five PCA compare/capture modules. —...
Page 413 REGISTERS Address: S:D9H CMOD Reset State: 00XX X000B PCA Timer/Counter Mode Register. Contains bits for selecting the PCA timer/counter input, disabling the PCA timer/counter during idle mode, enabling the PCA WDT reset output (module 4 only), and enabling the PCA timer/counter overflow interrupt. CIDL WDTE —...
Page 414 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:83H Reset State: 0000 0000B Data Pointer High. DPH provides SFR access to register file location 58 (also named DPH). DPH is ® the upper byte of the 16-bit data pointer, DPTR. Instructions in the MCS 51 architecture use DPTR for data moves, code moves, and for a jump instruction (JMP @A+DPTR).
Page 415 REGISTERS Address: S:84H DPXL Reset State: 0000 0001B Data Pointer Extended Low. DPXL provides SFR access to register file location 57 (also named DPXL). Location 57 is the lower byte of the upper word of the extended data pointer, DPX = DR56, whose lower word is the 16-bit data pointer, DPTR.
Page 416 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:A8H Reset State: 0000 0000B Interrupt Enable Register 0. IE0 contains two types of interrupt enable bits. The global enable bit (EA) enables/disables all of the interrupts, except the TRAP interrupt, which is always enabled. The remaining bits enable/disable the other individual interrupts.
Page 417 REGISTERS Address: S:B7H IPH0 Reset State: X000 0000B Interrupt Priority High Control Register 0. IPH0, together with IPL0, assigns each interrupt a priority level from 0 (lowest) to 3 (highest): IPH0. x IPL0. x Priority Level 0 (lowest priority) 3 (highest priority) —...
Page 418 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:B8H IPL0 Reset State: X000 0000B Interrupt Priority Low Control Register 0. IPL0, together with IPH0, assigns each interrupt a priority level from 0 (lowest) to 3 (highest): IPH0. x IPL0. x Priority Level...
Page 419 REGISTERS Address: S:80H Reset State: 1111 1111B Port 0. P0 is the SFR that contains data to be driven out from the port 0 pins. Read-modify-write instructions that read port 0 read this register. The other instructions that read port 0 read the port 0 pins.
Page 420 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:A0H Reset State: 1111 1111B Port 2. P2 is the SFR that contains data to be driven out from the port 2 pins. Read-modify-write instructions that read port 2 read this register. Other instructions that read port 2 read the port 2 pins.
Page 421 REGISTERS Address: S:87H PCON Reset State: 00XX 0000B Power Control Register. Contains the power off flag (POF) and bits for enabling the idle and powerdown modes. Also contains two general-purpose flags and two bits that control serial I/O functions—the double baud rate bit and a bit that selects whether accesses to SCON.7 are to the FE bit or the SM0 bit.
Page 422 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:D0H Reset State: 0000 0000B Program Status Word. PSW contains bits that reflect the results of operations, bits that select the register bank for registers R0–R7, and two general-purpose flags that are available to the user.
Page 423 REGISTERS Address: S:D1H PSW1 Reset State: 0000 0000B Program Status Word 1. PSW1 contains bits that reflect the results of operations and bits that select the register bank for registers R0–R7. — Function Number Mnemonic Carry Flag: Identical to the CY bit in the PSW register. Auxiliary Carry Flag: Identical to the AC bit in the PSW register.
Page 424 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:A9H SADDR Reset State: 0000 0000B Slave Individual Address Register. SADDR contains the device’s individual address for multiprocessor communication. Slave Individual Address Function Number Mnemonic SADDR.7:0 C-22...
Page 425 REGISTERS Address: S:B9H SADEN Reset State: 0000 0000B Mask Byte Register. This register masks bits in the SADDR register to form the device’s given address for multiprocessor communication. Mask for SADDR Function Number Mnemonic SADEN.7:0 Address: S:99H SBUF Reset State: XXXX XXXXB Serial Data Buffer.
Page 426 8XC251SA, SB, SP, SQ USER’S MANUAL Address: SCON Reset State: 0000 0000B Serial Port Control Register. SCON contains serial I/O control and status bits, including the mode select bits and the interrupt flag bits. FE/SM0 Function Number Mnemonic Framing Error Bit: To select this function, set the SMOD0 bit in the PCON register.
Page 427 REGISTERS Address: SCON Reset State: 0000 0000B Serial Port Control Register. SCON contains serial I/O control and status bits, including the mode select bits and the interrupt flag bits. FE/SM0 Function Number Mnemonic Transmit Interrupt Flag Bit: Set by the transmitter after the last data bit is transmitted. Cleared by software.
Page 428 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:BEH Reset State: 0000 0000B Stack Pointer High. SPH provides SFR access to location 62 in the register file (also named SPH). SPH is the upper byte of the lower word of DR60, the extended stack pointer (SPX). The extended stack pointer points to the current top of stack.
Page 429 REGISTERS Address: S:C8H T2CON Reset State: 0000 0000B Timer 2 Control Register. Contains the receive clock, transmit clock, and capture/reload bits used to configure timer 2. Also contains the run control bit, counter/timer select bit, overflow flag, external flag, and external enable for timer 2. EXF2 RCLK TCLK...
Page 430 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:C9H T2MOD Reset State: XXXX XX00B Timer 2 Mode Control Register. Contains the timer 2 down count enable and clock-out enable bits for timer 2 . — — — — — — T2OE...
Page 431 REGISTERS Address: S:88H TCON Reset State: 0000 0000B Timer/Counter Control Register. Contains the overflow and external interrupt flags and the run control and interrupt transition select bits for timer 0 and timer 1. Function Number Mnemonic Timer 1 Overflow Flag: Set by hardware when the timer 1 register overflows.
Page 432 8XC251SA, SB, SP, SQ USER’S MANUAL Address: S:89H TMOD Reset State: 0000 0000B Timer/Counter Mode Control Register. Contains mode select, run control select, and counter/timer select bits for controlling timer 0 and timer 1. GATE1 C/T1# GATE0 C/T0# Function Number...
Page 433 REGISTERS Address: TH0 S:8CH TH0, TL0 TL0 S:8AH Reset State: 0000 0000B TH0, TL0 Timer Registers. These registers operate in cascade to form the 16-bit timer register in timer 0 or separately as 8-bit timer/counters. High/Low Byte of Timer 0 Register Function Number Mnemonic...
Page 434 8XC251SA, SB, SP, SQ USER’S MANUAL Address: TH2 S:CDH TH2, TL2 TL2 S:CCH Reset State: 0000 0000B TH2, TL2 Timer Registers. These registers operate in cascade to form the 16-bit timer register in timer High/Low Byte of Timer 2 Register...
Page 435 REGISTERS Address: S:A6H WDTRST Reset State: XXXX XXXXB Watchdog Timer Reset Register. Writing the two-byte sequence 1EH-E1H to the WDTRST register clears and enables the hardware WDT. The WDTRST register is a write-only register. Attempts to read it return FFH. The WDT itself is not read or write accessible. See section 8.7, “Watchdog Timer.” WDTRST Contents (Write-only) Function Number...
Page 437 Glossary...
Page 439 GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this man- ual. (Chapter 1, “Guide to this Manual,” discusses notational conventions and general terminol- ogy.) #0data16 A 32-bit constant that is immediately addressed in an instruction. The upper word is filled with zeros. #1data16 A 32-bit constant that is immediately addressed in an instruction.
Page 440 8XC251SA, SB, SP, SQ USER’S MANUAL big endien form Memory storage format in which the most significant byte (MSB) of the word or double word is stored in the memory byte specified in the instruction. The remaining bytes are stored at higher addresses, with the least significant byte (LSB) at the highest address.
Page 441 GLOSSARY deassert The term deassert refers to the act of making a signal inactive (disabled). The polarity (high/low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To deassert RD# is to drive it high; to deassert ALE is to drive it low.
Page 442 8XC251SA, SB, SP, SQ USER’S MANUAL interrupt handler The module responsible for handling interrupts that are to be serviced by user-written interrupt service routines. interrupt latency The delay between an interrupt request and the time when the first instruction in the interrupt service routine begins execution.
Page 443 256-byte “page” of memory require only a one-state bus cycle. Program counter. peripheral cycle The cycle at which the 8XC251SA, SB, SP, SQ peripherals operate. This is equal to six state times. program memory A part of memory where instructions can be stored for fetching and execution.
Page 444 8XC251SA, SB, SP, SQ USER’S MANUAL The term set refers to the value of a bit or the act of giving it a value. If a bit is set, its value is “1”; setting a bit gives it a “1” value.
Page 445 GLOSSARY word A 16-bit unit of data. In memory, a word comprises two contiguous bytes. wraparound The result of interpreting an address whose hexadecimal expression uses more bits than the number of available address lines. Wraparound ignores the upper address bits and directs access to the value expressed by the lower bits.
Page 447 Index...
Page 449 ANL instruction, 5-9, 5-11 definition, A-3 for bits, A-23 #data16, A-3 ANL/ instruction, 5-11 #short, A-3 for bits, A-23 8XC251SA, SB, SP, SQ, 1-1 Arithmetic instructions, 5-8, 5-9 block diagram, 2-2 table of, A-14, A-15, A-16 on-chip peripherals, 2-3 8XC251Sx, 1-1 8XC51FX, 2-1...
Page 450 8XC251SA, SB, SP, SQ USER’S MANUAL CJNE instruction, A-25 CPL instruction, 5-9, 5-11, A-17, A-23 Clock, 2-6 CPU, 2-5 external, 11-4, 11-5 block diagram, 2-5 external source, 11-3 Crystal idle and powerdown modes, 12-5 for on-chip oscillator, 11-3 idle mode, 12-4...
Page 451 INDEX ECI, 7-1 EJMP instruction, 5-15, A-24 Given address, See Serial I/O port EMAP# bit, 3-9, 4-16 Ground bounce, 11-2 Encryption, 14-2 Encryption array key bytes, 14-8 Hardware programming, 14-1, 14-8 application notes, 1-6 setup for programming, 14-4–14-5 Help desk, 1-7 ERET instruction, 5-15, A-24 Escape prefix (A5H), 4-14 Extended stack pointer, See SPX...
Page 452 8XC251SA, SB, SP, SQ USER’S MANUAL detection, 6-3 JSLE instruction, A-25 edge-triggered, 6-4 Jump instructions enable/disable, 6-5 bit-conditional, 5-14 exiting idle mode, 12-5 compare-conditional, 5-14 exiting powerdown mode, 12-6 unconditional, 5-15 external, 6-3, 6-11 JZ instruction, A-24 global enable, 6-5 instruction completion time, 6-10 latency, 6-9–6-13...
Page 453 INDEX for bits, A-23 Oscillator, 2-6 N flag, 5-9, 5-19 at startup, 11-7 Noise reduction, 11-2, 11-3, 11-5 during reset, 11-5 Nonpage mode on-chip, 11-3 bus cycles, See External bus cycles, Nonpage ONCE mode, 12-7 mode powerdown mode, 12-5, 12-6 bus structure, 13-1 programming and verifying nonvolatile configuration, 4-8...
Page 454 8XC251SA, SB, SP, SQ USER’S MANUAL Phone numbers, customer support, 1-7 ports 1, 2, 3, 7-6 Pin conditions, 12-3 Pulse width measurements, 8-10 Pins PUSH instruction, 3-15, 5-10, A-22 unused inputs, 11-2 Pipeline, 2-5 POP instruction, 3-15, 5-10, A-22 Quick-pulse algorithm, 14-1...
Page 455 INDEX RETI instruction, 6-1, 6-14, 6-15, A-24 full-duplex, 10-6 Return instructions, 5-15 given address, 10-8 RL instruction, A-17 half-duplex, 10-4 RLC instruction, A-17 interrupts, 10-1, 10-8 ROM (on-chip), 14-1 mode 0, 10-4–10-5 verifying, 14-1–14-9 modes 1, 2, 3, 10-6 See also On-chip code memory, Configuration multiprocessor communication, 10-7 bytes, Lock bits, Encryption array, SFRs, 3-19, 10-1, 10-2, C-4...
Page 456 8XC251SA, SB, SP, SQ USER’S MANUAL T2, 7-1, 8-3 SFRs, 3-19, C-4 T2CON, 3-17, 3-19, 8-1, 8-2, 8-10, 8-17, 10-13, C- signal descriptions, 8-3 2, C-4, C-27 See also Timer 0, Timer 1, Timer 2 baud rate generator, 10-12 TMOD, 3-17, 3-19, 8-1, 8-2, 8-3, 8-6, 8-7, 10-11,...
Page 457 INDEX SFR (WDTRST), 3-19, C-4 WCLK (Wait Clock) Output, 13-2 WCON, 3-17, 13-11, C-2, C-3, C-32 WDTRST, 3-17, 3-19, 8-2, 8-16, C-2, C-4, C-33 World Wide Web, 1-7 WR#, 7-1 described, 13-2 XALE# bit, 4-13 XCH instruction, 5-10, A-22 XCHD instruction, 5-10, A-22 XRL instruction, 5-9 XTAL1, XTAL2, 11-3 capacitance loading, 11-5...

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8xc251sb 8xc251sp 8xc251sq

Intel 8XC251SA User Manual

Chapter 1 Guide to this Manual

Chapter 2 Architectural Overview

Chapter 3 Address Spaces

Chapter 4 Device Configuration

Chapter 5 Programming

Chapter 6 Interrupt System

Chapter 7 Input/Output Ports

Chapter 8 Timer/Counters and Watchdog Timer

Chapter 9 Programmable Counter Array

Chapter 10 Serial I/O Port

Chapter 11 Minimum Hardware Setup

Chapter 12 Special Operating Modes

Chapter 13 External Memory Interface

Chapter 14

Appendix A Instruction Set Reference

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Summary of Contents for Intel 8XC251SA