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12.8 FLOW DIAGRAMS
The flow diagrams in this section describe the steps that your software (shown as CPU) and the
CAN controller execute to receive and transmit messages. Table 12-13 lists the register bits
shown in the diagrams along with their associated registers and a cross-reference to the figure that
describes them.
Table 12-13. Cross-reference for Register Bits Shown in Flowcharts
Bit Mnemonic Register Mnemonic
CPUUPD
DIR
DLC
ID
INT_PND
MSGLST
MSGVAL
NEWDAT
RMTPND
RXIE
TXIE
TX_REG
XTD
CAN SERIAL COMMUNICATIONS CONTROLLER
CAN_MSG x CON1
Figure 12-15 on page 12-26
CAN_MSG x CFG
Figure 12-12 on page 12-21
CAN_MSG x CFG
Figure 12-12 on page 12-21
CAN_MSG x ID
Figure 12-13 on page 12-22
CAN_MSG x CON0
Figure 12-14 on page 12-24
CAN_MSG x CON1
Figure 12-15 on page 12-26
CAN_MSG x CON0
Figure 12-14 on page 12-24
CAN_MSG x CON1
Figure 12-15 on page 12-26
CAN_MSG x CON1
Figure 12-15 on page 12-26
CAN_MSG x CON0
Figure 12-14 on page 12-24
CAN_MSGxCON0
Figure 12-14 on page 12-24
CAN_MSG x CON1
Figure 12-15 on page 12-26
CAN_MSG x CFG
Figure 12-12 on page 12-21
Figure and Page
12-35
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