Intel 8XC196K Series User Manual page 251

8XC196K x , J x , CA USER'S MANUAL
INIT_INTERRUPTS:
LD JTBASE_PTR,#LSW JTBASE
EPAx_ISR:
LD EPAIPV_PTR,#EPAIPV
PUSHA
TIJMP JTBASE_PTR,[EPAIPV_PTR],#1FH
OVR_EPA0_ISR:
.
.
TIJMP JTBASE_PTR,[EPAIPV_PTR],#1FH
EPAx_DONE:
POPA
RET
JTBASE:
DCW LSW EPAx_done
DCW LSW OVR_TM2_ISR
DCW LSW OVR_TM1_ISR
DCW .
DCW .
DCW .
DCW LSW OVR_EPA0_ISR
This example assumes that EPAx is enabled, OVR0 is enabled, interrupts are globally enabled,
and the capture/compare channel 0 has generated an OVR0 interrupt. This interrupt occurs when
an edge is detected on the EPA channel and both the input buffer and EPA0_TIME are full. This
causes software to enter the EPAx_ISR interrupt service routine.
Note that index_mask is set to 1FH . This sets the pointer to the end of the jump table to prevent
software from jumping to an invalid address. Changing index_mask can dictate software control,
thus superseding interrupt priorities.
Note that instead of a RET instruction at the end of OVR_EPA0_ISR, another TIJMP instruction
is used. This is done to check for any other pending multiplexed interrupts. If EPAIPV contains
a zero value (no pending interrupts) a vector to EPAx_DONE occurs and a RET is executed. This
is to ensure that EPAIPV is cleared before the routine returns from the EPAx_ISR.
10-32
;store jump table base address
;read EPAIPV offset
;save INT_MASK/INT_MASK1/WSR/PSW
;initiate jump to correct ISR
;EPA0 overrun routine
;
;
;check for pending
;interrupts, exit
;exit, all EPAx
;interrupts serviced
;0 (no interrupt pending)
;1 (Timer2 overflow)
;2 (Timer1 overflow)
;0EH (EPA0 overflow)