Intel 8XC196K Series User Manual page 520

Name Type
†
WRH# O
WRL# O
XTAL1 I
XTAL2 O
†
This signal is not implemented on the 8XC196J x or 87C196CA (see "Design Considerations for
8XC196JQ, JR, JT, and JV Devices" on page 2-14 or "Design Considerations for 87C196CA Devices" on
page 2-13).
††
This signal is not implemented on the 8XC196J x (see "Design Considerations for 8XC196JQ, JR, JT, and
JV Devices" on page 2-14).
B.4 DEFAULT CONDITIONS
Table B-8 lists the default functions of the I/O and control pins of the 8XC196Kx with their values
during various operating conditions. Tables B-9 and B-10 list the same information for the
8XC196Jx and 87C196CA, respectively. Table B-7 defines the symbols used to represent the pin
status. Refer to the DC Characteristics table in the datasheet for actual specifications for V
V , and V .
OH IH
Symbol
0 Voltage less than or equal to V
1 Voltage greater than or equal to V
HiZ High impedance
LoZ0 Low impedance; strongly driven low
LoZ1 Low impedance; strongly driven high
Table B-6. Signal Descriptions (Continued)
Write High
The chip configuration register 0 (CCR0) determines whether this pin functions
as BHE# or WRH#. CCR0.2=1 selects BHE#; CCR0.2=0 selects WRH#.
During 16-bit bus cycles, this active-low output signal is asserted for high-byte
writes and word writes to external memory. During 8-bit bus cycles, WRH# is
asserted for all write operations.
WRH# is multiplexed with P5.5 and BHE#.
Write Low
The chip configuration register 0 (CCR0) determines whether this pin functions
as WR# or WRL#. CCR0.2=1 selects WR#; CCR0.2=0 selects WRL#.
During 16-bit bus cycles, this active-low output signal is asserted for low-byte
writes and word writes. During 8-bit bus cycles, WRL# is asserted for all write
operations.
WRL# is multiplexed with P5.2, SLPWR#, and WR#.
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator and the internal clock generators. The internal
clock generators provide the peripheral clocks, CPU clock, and CLKOUT
signal. When using an external clock source instead of the on-chip oscillator,
connect the clock input to XTAL1. The external clock signal must meet the V
specification for XTAL1 (see datasheet).
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses a external clock source instead of the on-chip oscillator.
Table B-7. Definition of Status Symbols
Definition
, V
OL IL
, V
OH IH
SIGNAL DESCRIPTIONS
Description
Symbol
MD0 Medium pull-down
MD1 Medium pull-up
WK0 Weak pull-down
WK1 Weak pull-up
ODIO Open-drain I/O
IH
, V ,
OL IL
Definition
B-19