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Page 1 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual Get other manuals https://www.bkmanuals.com...
Page 2 We Value Your Opinion Dear Intel Customer: We have updated the information that was provided in the 1992 version of the 8XC196MC User’s Manual, added information about the 8XC196MD and 8XC196MH, and corrected known errata. We hope these changes make it easier for you to use our products. Your feedback will help us to provide the information you need.
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Page 4 8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual August 2004 Order Number 272181-003 Get other manuals https://www.bkmanuals.com...
Page 5 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products.
Page 6: Table Of Contents
CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL MANUAL CONTENTS ....................1-1 NOTATIONAL CONVENTIONS AND TERMINOLOGY ..........1-3 RELATED DOCUMENTS ....................1-5 ELECTRONIC SUPPORT SYSTEMS ................1-8 1.4.4 World Wide Web .....................1-11 TECHNICAL SUPPORT ....................1-11 PRODUCT LITERATURE.................... 1-11 CHAPTER 2 ARCHITECTURAL OVERVIEW TYPICAL APPLICATIONS.....................
Page 7 8XC196MC, MD, MH USER’S MANUAL CHAPTER 3 PROGRAMMING CONSIDERATIONS OVERVIEW OF THE INSTRUCTION SET..............3-1 3.1.1 BIT Operands ......................3-2 3.1.2 BYTE Operands ......................3-2 3.1.3 SHORT-INTEGER Operands ..................3-2 3.1.4 WORD Operands ......................3-2 3.1.5 INTEGER Operands ....................3-3 3.1.6 DOUBLE-WORD Operands ..................3-3 3.1.7 LONG-INTEGER Operands ..................3-4...
Page 8 CONTENTS 4.1.5.1 Memory-mapped SFRs ..................4-5 4.1.5.2 Peripheral SFRs ....................4-5 4.1.6 Register File ......................4-9 4.1.6.1 General-purpose Register RAM .................4-10 4.1.6.2 Stack Pointer (SP) ....................4-10 4.1.6.3 CPU Special-function Registers (SFRs) .............4-11 WINDOWING....................... 4-12 4.2.1 Selecting a Window ....................4-13 4.2.2 Addressing a Location Through a Window .............4-14 4.2.2.1 32-byte Windowing Example ................4-16 4.2.2.2...
Page 9 8XC196MC, MD, MH USER’S MANUAL 5.6.6 Serial I/O Modes .....................5-37 5.6.6.1 Synchronous SIO Transmit Mode Example ............5-43 5.6.6.2 Synchronous SIO Receive Mode Example ............5-47 5.6.6.3 Asynchronous SIO Transmit Mode Example .............5-50 5.6.6.4 Asynchronous SIO Receive Mode Example ............5-55 CHAPTER 6 I/O PORTS I/O PORTS OVERVIEW ....................
Page 10 CONTENTS 7.4.5 Determining Serial Port Status ................7-15 CHAPTER 8 FREQUENCY GENERATOR FUNCTIONAL OVERVIEW.................... 8-1 PROGRAMMING THE FREQUENCY GENERATOR ........... 8-3 8.2.1 Configuring the Output ....................8-3 8.2.2 Programming the Frequency ..................8-3 8.2.3 Determining the Current Value of the Down-counter ..........8-4 APPLICATION EXAMPLE ..................... 8-4 CHAPTER 9 WAVEFORM GENERATOR WAVEFORM GENERATOR FUNCTIONAL OVERVIEW..........
Page 11 8XC196MC, MD, MH USER’S MANUAL 10.5.2 Reading the Current Value of the Down-counter ............10-7 10.5.3 Enabling the PWM Outputs ..................10-8 10.5.4 Generating Analog Outputs ..................10-10 CHAPTER 11 EVENT PROCESSOR ARRAY (EPA) 11.1 EPA FUNCTIONAL OVERVIEW ................. 11-1 11.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS ........11-2 11.3...
Page 12 CONTENTS 12.6.1.4 Using Mixed Analog and Digital Inputs ............12-13 12.6.2 Understanding A/D Conversion Errors ..............12-13 CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS 13.1 MINIMUM CONNECTIONS ..................13-1 13.1.1 Unused Inputs ......................13-2 13.1.2 I/O Port Pin Connections ..................13-2 13.2 APPLYING AND REMOVING POWER ............... 13-4 13.3 NOISE PROTECTION TIPS ..................
Page 13 8XC196MC, MD, MH USER’S MANUAL 15.4 WAIT STATES (READY CONTROL)................. 15-17 15.5 BUS-CONTROL MODES................... 15-21 15.5.1 Standard Bus-control Mode ..................15-22 15.5.2 Write Strobe Mode ....................15-25 15.5.3 Address Valid Strobe Mode ..................15-27 15.5.4 Address Valid with Write Strobe Mode ..............15-30 15.6 SYSTEM BUS AC TIMING SPECIFICATIONS ............
Page 14 CONTENTS APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS SIGNAL NAME CHANGES................... B-1 FUNCTIONAL GROUPINGS OF SIGNALS ..............B-1 SIGNAL DESCRIPTIONS................... B-12 DEFAULT CONDITIONS .................... B-22 APPENDIX C REGISTERS GLOSSARY INDEX Get other manuals https://www.bkmanuals.com...
Page 15 8XC196MC, MD, MH USER’S MANUAL FIGURES Figure Page 8XC196M x Block Diagram ...................2-3 Block Diagram of the Core ...................2-3 Clock Circuitry ......................2-7 Internal Clock Phases ....................2-8 Register File Memory Map ...................4-9 Windowing ........................4-12 Window Selection (WSR) Register................4-13 Flow Diagram for PTS and Standard Interrupts ............5-2 Waveform Generator Protection Circuitry..............5-7...
Page 16 CONTENTS FIGURES Figure Page Serial Port Frames in Mode 2 and 3................7-9 Serial Port Control (SP x _CON) Register..............7-10 Serial Port x Baud Rate (SP x _BAUD) Register............7-12 Serial Port Status (SP x _STATUS) Register ...............7-15 Frequency Generator Block Diagram ................8-1 Frequency (FREQ_GEN) Register ................8-3 Frequency Generator Count (FREQ_CNT) Register............8-4 Infrared Remote Control Application Block Diagram ............8-5...
Page 17 BUSWIDTH Timing Diagram (8XC196MH)..............15-12 15-6 Timings for 16-bit Buses...................15-15 15-7 Timings for 8-bit Buses.....................15-17 15-8 READY Timing Diagram — One Wait State (8XC196MC, MD) .......15-19 15-9 READY Timing Diagram — One Wait State (8XC196MH)........15-20 15-10 Standard Bus Control ....................15-22 15-11 Decoding WRL# and WRH#..................15-22...
Page 18 16-14 PCCB and UPROM Programming Circuit ..............16-31 16-15 Run-time Programming Code Example..............16-33 8XC196MC 64-lead Shrink DIP (SDIP) Package ............B-3 8XC196MC 84-lead PLCC Package ................B-4 8XC196MC 80-lead Shrink EIAJ/QFP Package............B-5 8XC196MD 84-lead PLCC Package ................B-7 8XC196MD 80-lead Shrink EIAJ/QFP Package............B-8 8XC196MH 64-lead Shrink DIP (SDIP) Package ............
Page 19 8XC196MC, MD, MH USER’S MANUAL TABLES Table Page Handbooks and Product Information ................1-6 Application Notes, Application Briefs, and Article Reprints ..........1-6 ® 96 Microcontroller Datasheets (Commercial/Express) ........1-7 ® 96 Microcontroller Datasheets (Automotive) .............1-7 ® 96 Microcontroller Quick References ..............1-8 Features of the 8XC196Mx Product Family..............2-2 State Times at Various Frequencies ................2-8...
Page 20 CONTENTS TABLES Table Page Control Register Values for Each Configuration............6-11 Port Configuration Example ..................6-11 6-10 Port Pin States After Reset and After Example Code Execution........6-12 6-11 Ports 3 and 4 Pins ......................6-14 6-12 Ports 3 and 4 Control and Status Registers ...............6-14 6-13 Logic Table for Ports 3 and 4 as Open-drain I/O............6-16 6-14...
Page 21 Description of Columns of Table B-6................. B-13 Signal Descriptions....................B-13 Definition of Status Symbols ..................B-23 8XC196MC and MD Default Signal Conditions ............B-23 8XC196MH Default Signal Conditions............... B-25 Modules and Related Registers .................. C-1 Register Name, Address, and Reset Status..............C-2 COMP x _TIME Addresses and Reset Values ............
Page 22: Guide To This Manual
Guide to This Manual Get other manuals https://www.bkmanuals.com...
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Page 24: Manual Contents
CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8XC196MC, 8XC196MD, and 8XC196MH embedded microcontrol- lers. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you com- plete your design.
Page 25 Chapter 9 — Waveform Generator — describes the waveform generator and explains how to configure it. For additional information and application examples, consult AP-483, Application Examples Using the 8XC196MC/MD Microcontroller (order number 272282). Chapter 10 — Pulse-width Modulator — provides a functional overview of the pulse width modulator (PWM) modules, describes how to program them, and provides sample circuitry for converting the PWM outputs to analog signals.
Page 26: Notational Conventions And Terminology
GUIDE TO THIS MANUAL Appendix C — Registers — provides a compilation of all device special-function registers (SFRs) arranged alphabetically by register mnemonic. It also includes tables that list the win- dowed direct addresses for all SFRs in each possible window. Glossary —...
Page 27 8XC196MC, MD, MH USER’S MANUAL numbers Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H. Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is appended to binary numbers for clarity.)
Page 28: Related Documents
For a complete list of available printed documents, please or- der the literature catalog (order number 210621). To order documents, please call the Intel literature center for your area (telephone numbers are listed on page 1-11).
Page 29 Complete set of Intel handbooks on CD-ROM. Handbook Set — handbooks and product overview 231003 Complete set of Intel’s product line handbooks. Contains datasheets, application notes, article reprints and other design information on microprocessors, periph- erals, embedded controllers, memory components, single-board computers, microcommunications, software development tools, and operating systems.
Page 30 †† AP-475, Using the 8XC196NT 272315 †† AP-477, Low Voltage Embedded Design 272324 AP-483, Application Examples Using the 8XC196MC/MD Microcontroller 272282 † AP-700, Intel Fuzzy Logic Tool Simplifies ABS Design 272595 AP-711, EMI Design Techniques for Microcontrollers in Automotive Applications 272324 ®...
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Page 32 GUIDE TO THIS MANUAL This Page Left Intentionally Blank Get other manuals https://www.bkmanuals.com...
Page 33 8XC196MC, MD, MH USER’S MANUAL This Page Left Intentionally Blank 1-10 Get other manuals https://www.bkmanuals.com...
Page 34: World Wide Web
GUIDE TO THIS MANUAL 1.4.4 World Wide Web We offer a variety of information through the World Wide Web (URL:http://www.intel.com/). Se- lect “Embedded Design Products” from the Intel home page. TECHNICAL SUPPORT In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m.
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Page 36: Architectural Overview
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Page 38: Typical Applications
CHAPTER 2 ARCHITECTURAL OVERVIEW The 16-bit 8XC196MC, 8XC196MD, and 8XC196MH CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output (I/O) operations. They share a common ® architecture and instruction set with other members of the MCS 96 microcontroller family.
Page 39: Functional Overview
80C196M x = none; 83C196M x = ROM; 87C196M x = OTPROM. Register RAM amounts include the 24 bytes allocated to core SFRs and the stack pointer. The 8XC196MC and 8XC196MD have no serial I/O ports, but have PTS modes that allow asynchro- nous or synchronous serial communication.
Page 40 ARCHITECTURAL OVERVIEW Optional Interrupt Core Controller Clock and Power Mgmt. Note: The frequency generator is unique to the 8XC196MD. The serial I/O port is unique to the 8XC196MH. A2798-02 Figure 2-1. 8XC196M x Block Diagram Memory Controller Register File RALU Prefetch Queue Microcode Engine...
Page 41: Cpu Control
8XC196MC, MD, MH USER’S MANUAL 2.3.1 CPU Control The CPU is controlled by the microcode engine, which instructs the RALU to perform operations using bytes, words, or double-words from either the 256-byte lower register file or through a win- dow that directly accesses the upper register file. (See Chapter 4, “Memory Partitions,” for more information about the register file and windowing.) CPU instructions move from the 4-byte...
Page 42: Code Execution
ARCHITECTURAL OVERVIEW The RALU uses the upper- and lower-word registers together for the 32-bit instructions and as temporary registers for many instructions. These registers have their own shift logic and are used for operations that require logical shifts, including normalize, multiply, and divide operations. The six-bit loop counter counts repetitive shifts.
Page 43: Memory Interface Unit
The PTS can transfer bytes or words, either individually or in blocks, between any memory loca- tions, manage multiple analog-to-digital (A/D) conversions, and can generate pulse-width mod- ulated (PWM) signals. The 8XC196MC and 8XC196MD have additional modes that allow asynchronous or synchronous serial communication. PTS interrupts have a higher priority than standard interrupts and may temporarily suspend interrupt service routines.
Page 44: Internal Timing
CPU Clocks (PH1, PH2) (Powerdown) Disable Clocks (Idle, Powerdown) NOTE: The CLKOUT pin is unique to the 8XC196MC and MD. A3115-02 Figure 2-3. Clock Circuitry The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-4). The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibil- ity in power management.
Page 45: Internal Peripherals
8XC196MC, MD, MH USER’S MANUAL XTAL1 XTAL1 XTAL1 1 State Time 1 State Time CLKOUT Phase 1 Phase 2 Phase 1 Phase 2 A0114-04 Figure 2-4. Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state.
Page 46: I/O Ports
Port 0 is an input-only port that is also the analog input for the A/D converter. On the 8XC196MH, port 0 provides two pins for the EPA. On the 8XC196MC and 8XC196MD, port 1 is also an input- only port that provides analog inputs for the A/D converter. On the 8XC196MH, port 1 is a bidi- rectional port that shares pins with the serial I/O port.
Page 47: Event Processor Array (Epa) And Timer/Counters
8XC196MC, MD, MH USER’S MANUAL 2.5.3 Event Processor Array (EPA) and Timer/Counters The event processor array (EPA) performs high-speed input and output functions associated with its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an event occurs, the EPA records the timer value associated with it.
Page 48: Analog-To-Digital Converter
ARCHITECTURAL OVERVIEW 2.5.7 Analog-to-digital Converter The analog-to-digital (A/D) converter converts an analog input voltage to a digital equivalent. Resolution is either 8 or 10 bits; sample and convert times are programmable. Conversions can be performed on the analog ground and reference voltage, and the results can be used to calculate gain and zero-offset errors.
Page 49: Programming The Nonvolatile Memory
• Slave programming allows a master EPROM programmer to program and verify one or more slave MCS 96 microcontrollers. Programming vendors and Intel distributors typically use this mode to program a large number of microcontrollers with a customer’s code and data.
Page 50: Programming Considerations
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Page 52: Overview Of The Instruction Set
CHAPTER 3 PROGRAMMING CONSIDERATIONS ® This section provides an overview of the instruction set of the MCS 96 microcontrollers and of- fers guidelines for program development. For detailed information about specific instructions, see Appendix A. INSTRUCTION SET OVERVIEW OF THE The instruction set supports a variety of operand types likely to be useful in control applications (see Table 3-1).
Page 53: Bit Operands
8XC196MC, MD, MH USER’S MANUAL Table 3-2 lists the equivalent operand-type names for both C programming and assembly lan- guage. Table 3-2. Equivalent Operand Types for Assembly and C Programming Languages Operand Types Assembly Language Equivalent C Programming Language Equivalent...
Page 54: Integer Operands
PROGRAMMING CONSIDERATIONS WORDs must be aligned at even byte boundaries in the address space. The least-significant byte of the WORD is in the even byte address, and the most-significant byte is in the next higher (odd) address. The address of a WORD is that of its least-significant byte (the even byte address). WORD operations to odd addresses are not guaranteed to operate in a consistent manner.
Page 55: Long-Integer Operands
8XC196MC, MD, MH USER’S MANUAL 3.1.7 LONG-INTEGER Operands A LONG-INTEGER is a 32-bit, signed variable that can take on values from –2,147,483,648 (– 2 ) through +2,147,483,647 (+2 –1). The architecture directly supports LONG-INTEGER operands only as the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product of 16-by-16 multiply operations.
Page 56: Addressing Modes
PROGRAMMING CONSIDERATIONS ADDRESSING MODES The instruction set uses four basic addressing modes: • direct • immediate • indirect (with or without autoincrement) • indexed (short-, long-, or zero-indexed) The stack pointer can be used with indirect addressing to access the top of the stack, and it can also be used with short-indexed addressing to access data within the stack.
Page 57: Direct Addressing
8XC196MC, MD, MH USER’S MANUAL Table 3-3. Definition of Temporary Registers Temporary Register Description word-aligned 16-bit register; AH is the high byte of AX and AL is the low byte word-aligned 16-bit register; BH is the high byte of BX and BL is the low byte word-aligned 16-bit register;...
Page 58: Indirect Addressing With Autoincrement
PROGRAMMING CONSIDERATIONS ; AL ← BL + MEM_BYTE(CX) ADDB AL,BL,[CX] ; MEM_WORD(AX) ← MEM_WORD(SP) [AX] ; SP ← SP + 2 3.2.3.1 Indirect Addressing with Autoincrement You can choose to automatically increment the indirect address after the current access. You spec- ify autoincrementing by adding a plus sign (+) to the end of the indirect reference.
Page 59: Long-Indexed Addressing
8XC196MC, MD, MH USER’S MANUAL The instruction LD AX,12H[BX] loads AX with the contents of the memory location that resides at address BX+12H. That is, the instruction adds the constant 12H (the offset) to the contents of BX (the base address), then loads AX with the contents of the resulting address. For example, if BX contains 1000H, then AX is loaded with the contents of location 1012H.
Page 60: Assembly Language Addressing Mode Selections
PROGRAMMING CONSIDERATIONS ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS The assembly language simplifies the choice of addressing modes. Use these features wherever possible. 3.3.1 Direct Addressing The assembly language chooses between direct and zero-indexed addressing depending on the memory location of the operand. Simply refer to the operand by its symbolic name. If the operand is in the lower register file, the assembly language chooses a direct reference.
Page 61: Addressing 32-Bit Operands
8XC196MC, MD, MH USER’S MANUAL To use these registers effectively, you must have some overall strategy for allocating them. The C programming language adopts a simple, effective strategy. It allocates the eight bytes beginning at address 1CH as temporary storage and treats the remaining area in the register file as a segment of memory that is allocated as required.
Page 62: Software Protection Features And Guidelines
PROGRAMMING CONSIDERATIONS If a procedure returns a value to the calling code (as opposed to modifying more global variables), the result is returned in the temporary storage space (TMPREG0, in this example) starting at 1CH. TMPREG0 is viewed as either an 8-, 16-, or 32bit variable, depending on the type of the proce- dure.
Page 63 8XC196MC, MD, MH USER’S MANUAL When using the watchdog timer (WDT) for software protection, we recommend that you reset the WDT from only one place in code, reducing the chance of an undesired WDT reset. The section of code that resets the WDT should monitor the other code sections for proper operation. This can be done by checking variables to make sure they are within reasonable values.
Page 64: Memory Partitions Memory Partitions
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Page 66: External Devices (Memory Or I/O)
CHAPTER 4 MEMORY PARTITIONS This chapter describes the address space, its major partitions, and a windowing technique for ac- cessing the upper register file and peripheral SFRs with register-direct instructions. MEMORY PARTITIONS Table 4-1 is a memory map of the 8XC196Mx devices. The remainder of this section describes the partitions.
Page 67: Program Memory
8XC196MC, MD, MH USER’S MANUAL Table 4-1. Memory Map Device and Hex Address Description Addressing Modes Range MC, MD FFFF FFFF External device (memory or I/O) connected to the Indirect or indexed 6000 A000 address/data bus 5FFF 9FFF Program memory (internal nonvolatile or external...
Page 68: Special-Purpose Memory
MEMORY PARTITIONS 4.1.4 Special-purpose Memory Special-purpose memory resides in locations 2000–207FH (Table 4-2). It contains several re- served memory locations, the chip configuration bytes (CCBs), and vectors for both peripheral transaction server (PTS) and standard interrupts. Accesses to this address range are directed to internal memory if EA# is held high and to external memory if EA# is held low.
Page 69: Security Key
8XC196MC, MD, MH USER’S MANUAL 4.1.4.3 Security Key The security key prevents unauthorized programming access to the nonvolatile memory. See Chapter 16, “Programming the Nonvolatile Memory,” for details. 4.1.4.4 Chip Configuration Bytes (CCBs) The chip configuration bytes (CCBs) specify the operating environment. They specify the bus width, bus-control mode, and wait states.
Page 70: Memory-Mapped Sfrs
Locations 1F00–1FDFH provide access to the peripheral SFRs. Table 4-6 on page 4-8, Table 4-6 on page 4-8, and Table 4-6 on page 4-8 list the peripheral SFRs of the 8XC196MC, 8XC196MD, and 8XC196MH, respectively. Locations that are omitted from the tables are reserved. The pe- ripheral SFRs are I/O control registers;...
Page 71 8XC196MC, MD, MH USER’S MANUAL Table 4-4. Peripheral SFRs — 8XC196MC Port 2 SFRs EPA and Timer SFRs Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte † 1FDEH Reserved Reserved 1F7EH TIMER2 (H) TIMER2 (L) •...
Page 72 MEMORY PARTITIONS Table 4-5. Peripheral SFRs — 8XC196MD Ports 2 and 7 SFRs EPA and Timer SFRs Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte † 1FDEH Reserved Reserved 1F7EH TIMER2 (H) TIMER2 (L) 1FDCH Reserved Reserved...
Page 73 8XC196MC, MD, MH USER’S MANUAL Table 4-6. Peripheral SFRs — 8XC196MH Port 0 and 2 SFRs Port 1 SFRs Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte 1FDEH Reserved Reserved 1F9EH P1_PIN Reserved 1FDCH...
Page 74: Register File
MEMORY PARTITIONS 4.1.6 Register File The register file (Figure 4-1) is divided into an upper register file and a lower register file. The upper register file consists of general-purpose register RAM. The lower register file contains gen- eral-purpose register RAM along with the stack pointer (SP) and the CPU special-function regis- ters (SFRs).
Page 75: Stack Pointer (Sp)
8XC196MC, MD, MH USER’S MANUAL Table 4-7. Register File Memory Addresses Device and Hex Address Range Description Addressing Modes MC, MD 01FF 02FF Upper register file (register RAM) Indirect, indexed, or windowed direct 0100 0100 00FF 00FF Lower register file (register RAM)
Page 76: Cpu Special-Function Registers (Sfrs)
The stack must be located in either the internal register file or external RAM. The stack can be used most efficiently when it is located in the register file. The following example initializes the top of the upper register file (8XC196MC, MD) as the stack. (For the 8XC196MH, the immediate value would be #300H.) SP, #200H ;Load stack pointer...
Page 77: Windowing
8XC196MC, MD, MH USER’S MANUAL WINDOWING Windowing expands the amount of memory that is accessible with register-direct addressing. Register-direct addressing can access the lower register file with short, fast-executing instruc- tions. With windowing, register-direct addressing can also access the upper register file and pe- ripheral SFRs.
Page 78: Selecting A Window
MEMORY PARTITIONS 4.2.1 Selecting a Window The window selection register (Figure 4-3) selects a window to be mapped into the top of the low- er register file. Table 4-9 provides a quick reference of WSR values for windowing the peripheral SFRs. Table 4-10 on page 4-14 lists the WSR values for windowing the upper register file.
Page 79: Addressing A Location Through A Window
8XC196MC, MD, MH USER’S MANUAL Table 4-10. Selecting a Window of the Upper Register File WSR Value WSR Value WSR Value Register RAM for 32-byte Window for 64-byte Window for 128-byte Window Locations (00E0–00FFH) (00C0–00FFH) (0080–00FFH) 8XC196MH Only 02E0–02FFH 02C0–02DFH 02A0–02BFH...
Page 80 MEMORY PARTITIONS Table 4-11. Windows WSR Value for WSR Value WSR Value Base 128-byte for 32-byte Window for 64-byte Window Address Window (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Peripheral SFRs 1FE0H 7FH (Note) 1FC0H 3FH (Note) 1FA0H 1F80H 1FH (Note) 1F60H 1F40H 1F20H 1F00H 02E0H 02C0H...
Page 81: 32-Byte Windowing Example
8XC196MC, MD, MH USER’S MANUAL Appendix C includes a table of the windowable SFRs with the WSR values and direct addresses for each window size. The following examples explain how to determine the WSR value and di- rect address for any windowable location. An additional example shows how to set up a window by using the linker locator.
Page 82: Using The Linker Locator To Set Up A Window
MEMORY PARTITIONS 4.2.2.5 Using the Linker Locator to Set Up a Window In this example, the linker locator is used to set up a window. The linker locator locates the win- dow in the upper register file and determines the value to load in the WSR for access to that win- dow.
Page 83 8XC196MC, MD, MH USER’S MANUAL wsr, #?WSR ;Prolog code for wsr add var1, var2, var3 wsr, [sp] ;Epilog code for wsr add sp, #2 ;Epilog code for wsr ****************************** The following is an example of a linker invocation to link and locate the modules and to deter- mine the proper windowing.
Page 84: Windowing And Addressing Modes
MEMORY PARTITIONS The C compiler can also take advantage of this feature if the “windows” switch is enabled. For details, see the MCS 96 microcontroller architecture software products in the Development Tools Handbook. 4.2.3 Windowing and Addressing Modes Once windowing is enabled, the windowed locations can be accessed both through the window using direct (8-bit) addressing and by the usual 16-bit addressing.
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Page 86: Standard And Pts Interrupts
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Page 88: Overview Of Interrupts
CHAPTER 5 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server (PTS) interrupts. It discusses the three special interrupts and the sev- en PTS modes, four of which are used with the EPA to provide a software serial I/O channel for both synchronous and asynchronous transfers and receptions.
Page 89 8XC196MC, MD, MH USER’S MANUAL Interrupt Pending or PTSSRV Bit Set Pending INT_MASK. x Return = 1? Interrupts Return Enabled? Enabled PTSSEL. x Bit = 1? Priority Encoder Highest Priority Interrupt Priority Encoder Highest Priority PTS Interrupt PTSSRV. x = 1? Reset INT_PEND.
Page 90: Interrupt Signals And Registers
STANDARD AND PTS INTERRUPTS Figure 5-1 illustrates the interrupt processing flow. In this flow diagram, “INT_MASK” repre- sents both the INT_MASK and INT_MASK1 registers, and “INT_PEND” represents both the INT_PEND and INT_PEND1 registers. INTERRUPT SIGNALS AND REGISTERS Table 5-1 describes the external interrupt signals and Table 5-2 describes the control and status registers for both the interrupt controller and PTS.
Page 91: Interrupt Sources And Priorities
8XC196MC, MD, MH USER’S MANUAL Table 5-2. Interrupt and PTS Control and Status Registers (Continued) Mnemonic Address Description PI_PEND 1FBEH Peripheral Interrupt Pending Any bit set indicates a pending interrupt request. No direct access Processor Status Word This register contains one bit that globally enables or disables servicing of all maskable interrupts and another that enables or disables the PTS.
Page 92 STANDARD AND PTS INTERRUPTS Table 5-3. Interrupt Sources, Vectors, and Priorities Interrupt Controller PTS Service Service Interrupt Source Mnemonic Nonmaskable Interrupt INT15 203EH — — — EXTINT Pin EXTINT INT14 203CH PTS14 205CH WF Gen (MC) † WF Gen & EPA Comp 5 (MD) INT13 203AH PTS13...
Page 93: Special Interrupts
8XC196MC, MD, MH USER’S MANUAL 5.3.1 Special Interrupts This microcontroller has three special interrupt sources that are always enabled: unimplemented opcode, software trap, and NMI. These interrupts are not affected by the EI (enable interrupts) and DI (disable interrupts) instructions, and they cannot be masked. All of these interrupts are serviced by the interrupt controller;...
Page 94: Multiplexed Interrupt Sources
PI_MASK register (Figure 5-9 on page 5-17). Figure 5-3 shows the flow for the timer interrupt. NOTE Although the PI interrupt on the 8XC196MC has a single source (the waveform generator), software must still enable both the source interrupt (WG) in the PI_PEND register and the PI interrupt in the INT_MASK register.
Page 95 8XC196MC, MD, MH USER’S MANUAL The interrupt service routine should read the PI_PEND (Figure 5-12 on page 5-23) register to de- termine the source of the interrupt. Before executing the return instruction, the interrupt service routine should check to see if any of the other interrupt sources are pending. Generally, PTS in- terrupt service is not useful for multiplexed interrupts because the PTS cannot readily determine the interrupt source.
Page 96: End-Of-Pts Interrupts
STANDARD AND PTS INTERRUPTS 5.3.4 End-of-PTS Interrupts When the PTSCOUNT register decrements to zero at the end of a single transfer, block transfer, A/D scan, or serial I/O routine, hardware clears the corresponding bit in the PTSSEL register, (Figure 5-6 on page 5-14) which disables PTS service for that interrupt. It also sets the corre- sponding PTSSRV bit, requesting an end-of-PTS interrupt.
Page 97: Calculating Latency
8XC196MC, MD, MH USER’S MANUAL Each PTS cycle within a PTS routine cannot be interrupted. A PTS cycle is the entire PTS re- sponse to a single interrupt request. In block transfer mode, a PTS cycle consists of the transfer of an entire block of bytes or words.
Page 98: Pts Interrupt Latency
STANDARD AND PTS INTERRUPTS 4 3 2 1 If Stack Ending Call is If Stack "NORML" Execution "PUSHA" Instruction "NORML" Forced External External Interrupt Routine EXTINT Pending Cleared Interrupt 56 State Times Response Time A0136-02 Figure 5-4. Standard Interrupt Response Time 5.4.2.2 PTS Interrupt Latency The maximum delay for a PTS interrupt is 43 state times (4 + 39) as shown in Figure 5-5.
Page 99: Programming The Interrupts
8XC196MC, MD, MH USER’S MANUAL Table 5-4. Execution Times for PTS Cycles PTS Mode Execution Time (in State Times) Single transfer mode † register/register 18 per byte or word transfer + 1 † memory/register 21 per byte or word transfer + 1 †...
Page 100 STANDARD AND PTS INTERRUPTS When you assign an interrupt to the PTS, you must set up a PTS control block (PTSCB) for each interrupt source (see “Initializing the PTS Control Blocks” on page 5-24) and use the EPTS in- struction to globally enable the PTS. When you assign an interrupt to a standard software service routine, use the EI (enable interrupts) instruction to globally enable interrupt servicing.
Page 101 PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts. † On the 8XC196MC device bits 10–12 are reserved. For compatibility with future devices, write zeros to these bits. Figure 5-6. PTS Select (PTSSEL) Register 5-14 Get other manuals https://www.bkmanuals.com...
Page 102 STANDARD AND PTS INTERRUPTS Address: 0008H INT_MASK Reset State: The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW). PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register.
Page 103 SIO 0 and SIO 1 can generate this interrupt. Write to PI_MASK to enable the interrupt sources; read PI_PEND to determine which source caused the interrupt. † On the 8XC196MC device bits 4–3 are reserved. For compatibility with future devices, write zeros to these bits. Figure 5-8. Interrupt Mask 1 (INT_MASK1) Register 5-16 Get other manuals https://www.bkmanuals.com...
Page 104 1FBCH PI_MASK Reset State: The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM). 8XC196MC — — — — OVRTM2 —...
Page 105: Modifying Interrupt Priorities
8XC196MC, MD, MH USER’S MANUAL Address: 1FBCH PI_MASK (Continued) Reset State: The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM).
Page 106 STANDARD AND PTS INTERRUPTS Note that location 2002H in the interrupt vector table must be loaded with the value of the label AD_DONE_ISR before the interrupt request occurs and that the A/D conversion complete inter- rupt must be enabled for this routine to execute. This routine, like all interrupt service routines, is handled in the following manner: After the hardware detects and prioritizes an interrupt request, it generates and executes an interrupt call.
Page 107: Determining The Source Of An Interrupt
8XC196MC, MD, MH USER’S MANUAL 5.5.2 Determining the Source of an Interrupt When hardware detects an interrupt, it sets the corresponding bit in the INT_PEND or INT_PEND1 register (Figures 5-10 and 5-11 ). It sets the bit even if the individual interrupt is disabled (masked).
Page 108 STANDARD AND PTS INTERRUPTS Address: 0009H INT_PEND Reset State: When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. MC, MD COMP2 EPA2...
Page 109 On the 8XC196MD, the waveform generator and the EPA compare channel 5 can generate this interrupt. Write to PI_MASK to enable the interrupt sources; read PI_PEND to determine which source caused the interrupt. On the 8XC196MC, the waveform generator is the sole source for this interrupt.
Page 110 (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit. Reading this register clears all the PI_PEND bits. Software can generate an interrupt by setting a PI_PEND bit. 8XC196MC — — —...
Page 111: Initializing The Pts Control Blocks
8XC196MC, MD, MH USER’S MANUAL Address: 1FBEH PI_PEND (Continued) Reset State: When hardware detects a pending peripheral or timer interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit.
Page 112: Specifying The Pts Count
PTSCOUNT PTSCOUNT PTSCOUNT PORTREG (L) † 8XC196MC and MD only. Figure 5-13. PTS Control Blocks 5.6.1 Specifying the PTS Count The first location of the PTSCB contains an 8-bit value called PTSCOUNT. This value defines the number of interrupts that will be serviced by the PTS routine. The PTS decrements PTSCOUNT after each PTS cycle.
Page 113 PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts. † On the 8XC196MC device bits 10–12 are reserved. These bits are undefined. Figure 5-14. PTS Service (PTSSRV) Register 5-26 Get other manuals https://www.bkmanuals.com...
Page 114: Selecting The Pts Mode
EPA to move captured time values from the event-time register to internal RAM for further processing. See AP-483, Application Examples Using the 8XC196MC/MD Microcontroller, for application examples with code. Figure 5-16 shows the PTS control block for single transfer mode.
Page 115 8XC196MC, MD, MH USER’S MANUAL PTS Single Transfer Mode Control Block In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). Unused Unused PTSDST (H)
Page 116 STANDARD AND PTS INTERRUPTS PTS Single Transfer Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode single transfer mode Byte/Word Transfer 0 = word transfer 1 = byte transfer † Update PTSSRC 0 = reload original PTS source address after each byte or word transfer 1 = retain current PTS source address after each byte or word...
Page 117: Block Transfer Mode
In block transfer mode, an interrupt causes the PTS to move a block of bytes or words from one memory location to another. See AP-483, Application Examples Using the 8XC196MC/MD Mi- crocontroller, for application examples with code. Figure 5-17 shows the PTS control block for block transfer modes.
Page 118 STANDARD AND PTS INTERRUPTS PTS Block Transfer Mode Control Block In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT). Unused PTSBLOCK PTS Block Size...
Page 119: A/D Scan Mode
8XC196MC, MD, MH USER’S MANUAL PTS Block Transfer Mode Control Block (Continued) Register Location Function PTSCON PTSCB + 1 PTS Control Bits M2:0 PTS Mode These bits select the PTS mode: block transfer mode Byte/Word Transfer 0 = word transfer...
Page 120 STANDARD AND PTS INTERRUPTS PTS A/D Scan Mode Control Block In A/D scan mode, the PTS causes the A/D converter to perform multiple conversions on one or more channels and then stores the results. The control block contains pointers to both the AD_RESULT register (PTSPTR1) and a table of A/D conversion commands and results (PTSPTR2), a control register (PTSCON), and an A/D conversion count (PTSCOUNT).
Page 121 See AP-483, Application Examples Using the 8XC196MC/MD Microcontroller, for application examples with code.
Page 122: A/D Scan Mode Cycles
STANDARD AND PTS INTERRUPTS 5.6.5.1 A/D Scan Mode Cycles Software must start the first A/D conversion. After the A/D conversion complete interrupt ini- tiates the PTS routine, the following actions occur. The PTS reads the first command (from address XXXX), stores it in a temporary location, and increments the PTSPTR1 register twice.
Page 123 8XC196MC, MD, MH USER’S MANUAL version. Step 4 updates PTSPTR1 (PTSPTR1 now points to 3004H) and step 5 decrements PTSCOUNT to 3. The next cycle begins by storing the channel 5 command in the temporary lo- cation. During the last cycle (PTSCOUNT = 1), the dummy command is loaded into the AD_COMMAND register and no conversion is performed.
Page 124: A/D Scan Mode Example 2
5.6.6 Serial I/O Modes The 8XC196MH has a two-channel serial I/O port. The 8XC196MC and MD have no serial I/O ports, but the serial I/O modes of the PTS provide a software serial I/O channel for both synchro- nous and asynchronous transfers and receptions. There are four basic modes of operation: syn- chronous transmit, synchronous receive, asynchronous transmit, and asynchronous receive.
Page 125 I/O modes require two PTS control blocks to configure all options (see Figures 5-19 and 5-20). These blocks need not be contiguous, but they must each be located in register RAM on a quad- word boundary. See AP-483, Application Examples Using the 8XC196MC/MD Microcontroller, for application examples with code.
Page 126 STANDARD AND PTS INTERRUPTS PTS Serial I/O Mode Control Block 1 (Continued) (8XC196MC, MD) Register Location Function BAUD PTSCB1 + 4 Baud Value This register contains the 16-bit value that the PTS uses to generate the desired baud rate. Use the following formula to calculate the value to load into the BAUD register.
Page 127 8XC196MC, MD, MH USER’S MANUAL PTS Serial I/O Mode Control Block 1 (Continued) (8XC196MC, MD) Register Location Function PTSCOUNT PTSCB1 + 0 Consecutive PTS Cycles Defines the number of bits to be transmitted or received, including parity and stop bits, but not the start bit. For asynchronous modes, program a number that is between 1–16.
Page 128 STANDARD AND PTS INTERRUPTS PTS Serial I/O Mode Control Block 2 (8XC196MC, MD) The PTS control block 2 contains pointers to both the port register (PORTREG) and the data register (DATA). It also contains a 16-bit value that is used to calculate the sample time for asynchronous receptions when majority sampling is selected (SAMPTIME), a control register (PTSCON1), and a 16- bit value that is used to select the port signal that functions as the TXD or RXD signal (PORTMASK).
Page 129 8XC196MC, MD, MH USER’S MANUAL PTS Serial I/O Mode Control Block 2 (Continued) (8XC196MC, MD) Register Location Function DATA PTSCB2 + 4 Data Register This 16-bit register holds the data to be transmitted or the data that has been received. During transmit mode, the least- significant bit (bit 0) is transmitted first.
Page 130: Synchronous Sio Transmit Mode Example
STANDARD AND PTS INTERRUPTS PTS Serial I/O Mode Control Block 2 (Continued) (8XC196MC, MD) Register Location Function PORTMASK PTSCB2 + 2 Port Mask Register Select the port signal that will function as the transmit data (TXD) or receive data (RXD) signal by setting the corresponding bit.
Page 131 8XC196MC, MD, MH USER’S MANUAL If the SCK signal is generated by the EPA channel, the first PTS cycle must be started manually. • Initialize the TXD port pin and the SCK signal to the system-required logic level before starting a transmission.
Page 132 STANDARD AND PTS INTERRUPTS Table 5-13. SSIO Transmit Mode PTSCBs PTSCB1 PTSCB2 PTSVEC (H) = pointer to PTSCB2 Unused PTSVEC (L) = pointer to PTSCB2 SAMPTIME = unused BAUD (H) = 00H (9600 baud at 16 MHz) DATA (H) = unused BAUD (L) = D0H (9600 baud at 16 MHz) DATA (L) = nn H (8 data bits) EPAREG (H) = 1FH (EPA0_TIME)
Page 133 8XC196MC, MD, MH USER’S MANUAL time into the event-time register. If this toggle occurs, the clock polarity will change because of the odd number of toggles and erroneous data may be output. The interrupt service routine should also load the next data byte, reload the PTSCOUNT and PTSCON1 registers, select PTS service for EPA0, reload both the EPA0_CONTROL and EPA0_TIME registers.
Page 134: Synchronous Sio Receive Mode Example
STANDARD AND PTS INTERRUPTS 5.6.6.2 Synchronous SIO Receive Mode Example In synchronous serial I/O (SSIO) receive mode, an EPA channel controls the reception baud rate by generating or capturing a serial clock signal (SCK). To generate the SCK signal, configure the EPA channel in compare mode and set the output-pin toggle option.
Page 135 8XC196MC, MD, MH USER’S MANUAL The following example uses EPA0 to capture the SCK signal and P2.3 to receive the data (RXD). It sets up a synchronous serial I/O PTS routine that receives 16 bytes with eight data bits. Because this example uses an external serial clock input, the TIMER1 and BAUD registers are not used.
Page 136 STANDARD AND PTS INTERRUPTS Select PTS service for EPA0. — Set PTSSEL.2. Set-up EPA0 to capture on both rising and falling edges. — Set EPA0_CON bits 4 and 5 (Figure 11-10 on page 11-19). 10. Enable the PTS and conventional interrupts. —...
Page 137: Asynchronous Sio Transmit Mode Example
8XC196MC, MD, MH USER’S MANUAL End-Of-PTS Interrupt Save Critical Data Disable EPA Channel Clear Interrupt Request Bit Save Received Data R_COUNT = R_COUNT - 1 R_COUNT = 0? Set-up next data reception - Clear DATA register - Reload PTSCOUNT and PTSCON1 registers...
Page 138 STANDARD AND PTS INTERRUPTS End-of-PTS Conventional 10 PTS Serviced Interrupts Interrupt Interrupts Software Clears TXD Parity Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Start Stop (Port pin) 1 Bit Time Optional Parity Bit A3119-01 Figure 5-25.
Page 139 8XC196MC, MD, MH USER’S MANUAL Initialize and enable the timer; select up counting, internal clock, and prescaler disabled. — Set T1CONTROL bits 6 and 7 (Figure 11-8 on page 11-16). Initialize the PTSCB as shown in Table 5-15. Table 5-15. ASIO Transmit Mode PTSCBs...
Page 140 STANDARD AND PTS INTERRUPTS 14. The transmission will begin. Data is shifted out with the least-significant (rightmost) bit first. Each time a timer match occurs between EPA0_TIME and TIMER1, the EPA0 channel generates an interrupt and the PTS outputs the next bit of data on the pin configured as TXD.
Page 141 8XC196MC, MD, MH USER’S MANUAL End-Of-PTS Interrupt Save Critical Data Is PTS Cycle Completed? Disable EPA Channel Clear Interrupt Request Bit T_COUNT = T_COUNT - 1 T_COUNT = 0? Set-up next data transfer - Load next data byte into DATA register...
Page 142: Asynchronous Sio Receive Mode Example
STANDARD AND PTS INTERRUPTS 5.6.6.4 Asynchronous SIO Receive Mode Example In asynchronous serial I/O (ASIO) receive mode, an EPA channel is set up to capture the falling edge when the data start bit toggles on a port pin that is configured to function as the Receive Data signal (RXD).
Page 143 8XC196MC, MD, MH USER’S MANUAL Set-up the stack pointer. Reset all interrupt mask registers. — Clear INT_MASK, INT_MASK1and PI_MASK. Initialize P2.0 to function as the RXD signal. — Set P2_DIR.0 (selects input). — Clear P2_MODE.0 (selects LSIO function). — Set P2_REG.0 (initializes RXD input to “1”).
Page 144 STANDARD AND PTS INTERRUPTS 11. Enable the PTS and conventional interrupts. — Use the EI instruction to enable all standard interrupts and the EPTS instruction to enable the PTS. 12. Toggle the RXD input to start the reception. The EPA will generate a conventional interrupt.
Page 145 8XC196MC, MD, MH USER’S MANUAL End-Of-PTS Interrupt Save Critical Data Start Bit? Disable EPA Channel Clear Interrupt Request Bit Start Bit Error? Framing Error? Initialize Parity Error? EPA Channel Set Time To First Save Received Data RXDDONE = 3 Bit Sample...
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Page 148: I/O Ports Overview
CHAPTER 6 I/O PORTS I/O ports provide a mechanism to transfer information between the device and the surrounding system circuitry. They can read system status, monitor system operation, output device status, configure system options, generate control signals, provide serial communication, and so on. Their usefulness in an application is limited only by the number of I/O pins available and the imagination of the engineer.
Page 149: Input-Only Ports 1 (Mc, Md Only) And 0
The input-only ports differ from the other standard ports in that their pins can be used only as in- puts to the digital or analog circuitry. On the 8XC196MC and 8XC196MD, port 1 is an input-only port that serves the same purpose as port 0. The 8XC196MC implements five pins, while the 8XC196MD implements all eight.
Page 150: Standard Input-Only Port Operation
I/O PORTS Table 6-3. Input-only Port Registers Mnemonic Address Description P0_PIN 1FA8H (MC, MD) Each bit of P0_PIN reflects the current state of the corresponding 1FDAH (MH) port 0 pin. P1_PIN (MC, MD) 1FA9H (MC, MD) Each bit of P1_PIN reflects the current state of the corresponding port 1 pin.
Page 151: Standard Input-Only Port Considerations
8XC196MC, MD, MH USER’S MANUAL 6.2.2 Standard Input-only Port Considerations Port 0 and 1 pins are unique in that they may individually be used as digital inputs and analog inputs at the same time. However, reading the port induces noise into the A/D converter, decreas- ing the accuracy of any conversion in progress.
Page 152 I/O PORTS Table 6-4. Bidirectional Port Pins Special-function Special-function Associated Port Pin Signal(s) Signal Type Peripheral P1.0 (MH) TXD0 P1.1 (MH) RXD0 P1.2 (MH) TXD1 P1.3 (MH) RXD1 P2.0 EPA0 EPA1 (MC, MD) P2.1 SCLK0# (MH) BCLK0 (MH) EPA2 (MC, MD) P2.2 EPA1 (MH) EPA3 (MC, MD)
Page 153: Bidirectional Port Operation
8XC196MC, MD, MH USER’S MANUAL Table 6-5 lists the registers associated with the bidirectional ports. Each port has three control reg- isters (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN regis- ter is a status register that returns the logic level present on the pins; it can only be read. The registers for the standard ports are byte-addressable and can be windowed.
Page 154 Q4 remains on, weakly holding the pin high, until your software writes to the Px_MODE register. NOTE (8XC196MC, MD Only) P2.7 is an exception. After reset, P2.7 carries the CLKOUT signal (half the crystal input frequency) rather than being held high. When CLKOUT is selected, it is always a complementary output.
Page 155 8XC196MC, MD, MH USER’S MANUAL Internal Bus Px_REG SFDATA I/O Pin Px_DIR SFDIR Px_MODE Sample 150Ω to 200Ω Latch Px_PIN Read Port PH1 Clock Medium Pullup 300ns Delay RESET# Weak RESET# Pullup Any Write to Px_MODE A0238-04 Figure 6-2. Bidirectional Port Structure...
Page 156: Bidirectional Port Pin Configurations
I/O PORTS Table 6-6. Logic Table for Bidirectional Ports in I/O Mode Open-drain Configuration Complementary Output Input Output P x _MODE P x _DIR SFDIR SFDATA P x _REG 0, 1 (Note 2) on, off (Note 2) P x _PIN X (Note 3) high impedance (Note 4) NOTES:...
Page 157 8XC196MC, MD, MH USER’S MANUAL To prevent the CMOS inputs from floating, the bidirectional port pins are weakly pulled high dur- ing and after reset, until your software writes to Px_MODE. The default values of the control reg- isters after reset configure the pins as high-impedance inputs with weak pull-ups. To ensure that...
Page 158: Bidirectional Port Pin Configuration Example
I/O PORTS Table 6-8. Control Register Values for Each Configuration Desired Pin Configuration Configuration Register Settings † Standard I/O Signal P x _DIR P x _MODE P x _REG Complementary output, driving 0 Complementary output, driving 1 Open-drain output, strongly driving 0 Open-drain output, high impedance Input †...
Page 159: Bidirectional Port Considerations
8XC196MC, MD, MH USER’S MANUAL Table 6-10. Port Pin States After Reset and After Example Code Execution † Resulting Pin States Action or Code P x .7 P x .6 P x .5 P x .4 P x .3 P x .2 P x .1...
Page 160 This pin is weakly held high until your software writes to P5_MODE. P5.4 is the enable pin for ONCE mode (see Chapter 14, “Special Operating Modes”) and one of the enable pins for Intel- reserved test modes. Because a low input during reset could cause the device to enter ONCE mode or a reserved test mode, exercise caution if you use this pin for input.
Page 161: Bidirectional Ports 3 And 4 (Address/Data Bus)
8XC196MC, MD, MH USER’S MANUAL BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS) Ports 3 and 4 are eight-bit, bidirectional, memory-mapped I/O ports. They can be addressed only with indirect or indexed addressing and cannot be windowed. Ports 3 and 4 provide the multi- plexed address/data bus.
Page 162: Bidirectional Ports 3 And 4 (Address/Data Bus) Operation
I/O PORTS 6.4.1 Bidirectional Ports 3 and 4 (Address/Data Bus) Operation Figure 6-3 shows the ports 3 and 4 logic. During reset, the active-low level of RESET# turns off Q1 and Q2 and turns on transistor Q3, which weakly pulls the pin high. (Q1 can source at least – 3 mA at V –0.7 volts;...
Page 163: Using Ports 3 And 4 As I/O
8XC196MC, MD, MH USER’S MANUAL Table 6-13. Logic Table for Ports 3 and 4 as Open-drain I/O Configuration Open-drain P x _REG P x_ PIN high impedance 6.4.2 Using Ports 3 and 4 as I/O To use a port pin as an output, write the output data to the corresponding Px_REG bit. When the device requires access to external memory, it takes control of the port and drives the address/data bit onto the pin.
Page 164: Output-Only Port Operation
I/O PORTS Table 6-14. Standard Output-only Port Pins Special-function Special-function Associated Port Pin Signal(s) Signal Type Peripheral P6.0 WG1# Output Waveform generator P6.1 Output Waveform generator P6.2 WG2# Output Waveform generator P6.3 Output Waveform generator P6.4 WG3# Output Waveform generator P6.5 Output Waveform generator...
Page 165 8XC196MC, MD, MH USER’S MANUAL Internal Bus WG_OUTPUT Output Pin Combinational Logic A2764-01 Figure 6-4. Output-only Port Address: 1FC0H WG_OUTPUT (Port 6) Reset State: 0000H The port 6 output configuration (WG_OUTPUT) register controls port 6 functions. If you are using port 6 for general-purpose outputs, write C0H (for active-high outputs) or 00H (for active-low outputs) to the high byte of WG_OUTPUT, and write the desired pin values to the low byte.
Page 166 I/O PORTS Address: 1FC0H WG_OUTPUT (Port 6) (Continued) Reset State: 0000H The port 6 output configuration (WG_OUTPUT) register controls port 6 functions. If you are using port 6 for general-purpose outputs, write C0H (for active-high outputs) or 00H (for active-low outputs) to the high byte of WG_OUTPUT, and write the desired pin values to the low byte.
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Page 168: Serial I/O (Sio) Port
Serial I/O (SIO) Port Get other manuals https://www.bkmanuals.com...
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Page 170: Serial I/O (Sio) Port Functional Overview
The 8XC196MH device has a two-channel serial I/O port that shares pins with ports 1 and 2. (The 8XC196MC and 8XC196MD devices do not have serial I/O ports.) This chapter de- scribes the SIO port and explains how to configure it. Chapter 6, “I/O Ports,” explains how to con- figure the port pins for their special functions.
Page 171: Serial I/O Port Signals And Registers
8XC196MC, MD, MH USER’S MANUAL An independent, 15-bit baud-rate generator controls the baud rate of the serial port. Either XTAL1 or BCLKx can provide the clock signal for modes 0–3. In mode 4, the internal shift clock is output on SCLKx# or an external shift clock is input on SCLKx# (in which case the baud-rate generator is not used).
Page 172 SERIAL I/O (SIO) PORT Table 7-2. Serial Port Control and Status Registers (Continued) Mnemonic Address Description INT_PEND1 0012H Interrupt Pending 1 When set, the TI x bit indicates a pending transmit interrupt. When set, the RI x bit indicates a pending receive interrupt. When set, the SPE bit indicates a pending serial port receive error interrupt.
Page 173: Serial Port Modes
8XC196MC, MD, MH USER’S MANUAL Table 7-2. Serial Port Control and Status Registers (Continued) Mnemonic Address Description PI_MASK 1FBCH Peripheral Interrupt Mask This register enables and disables multiplexed peripheral interrupts. Setting an SP x bit enables a serial port receive error interrupt;...
Page 174: Synchronous Modes (Modes 0 And 4)
SERIAL I/O (SIO) PORT 7.3.1 Synchronous Modes (Modes 0 and 4) The 8XC196MH serial port has two synchronous modes, mode 0 and mode 4. Mode 0 is the syn- chronous mode available on all the 8XC196 devices that have serial ports. Mode 4 is an enhanced, full-duplex synchronous mode.
Page 175: Mode 4
8XC196MC, MD, MH USER’S MANUAL During a reception, the RI flag in SPx_STATUS is set after the stop bit is sampled. The RIx pend- ing bit in the interrupt pending register is set immediately before the RI flag is set. During a trans- mission, the TI flag is set immediately after the end of the last (eighth) data bit is transmitted.
Page 176: Asynchronous Modes (Modes 1, 2, And 3)
SERIAL I/O (SIO) PORT In mode 4, writing to SBUFx_TX starts a transmission regardless of whether RXDx is enabled. However, RXDx must be enabled to allow a reception. If RXDx is enabled, either a rising edge on the RXDx input or clearing the receive interrupt (RI) flag starts a reception. Disabling RXDx stops a reception in progress and inhibits further receptions.
Page 177: Mode 2
8XC196MC, MD, MH USER’S MANUAL Stop Start Stop 8 Bits of Data or 7 Bits of Data with Parity Bit 10-bit Frame A0245-02 Figure 7-4. Serial Port Frames for Mode 1 The transmit and receive functions are controlled by separate shift clocks. The transmit shift clock starts when the baud-rate generator is initialized.
Page 178: Mode 3
SERIAL I/O (SIO) PORT Stop Stop Start 8 Bits of Data Programmable 9th Bit 11-bit Frame A0111-01 Figure 7-5. Serial Port Frames in Mode 2 and 3 7.3.2.3 Mode 3 Mode 3 is the asynchronous, ninth-bit mode. The data frame for this mode is identical to that of mode 2.
Page 179: Programming The Serial Port
8XC196MC, MD, MH USER’S MANUAL PROGRAMMING THE SERIAL PORT To use the SIO port, you must configure the port pins to serve as special-function signals and set up the SIO channels. 7.4.1 Configuring the Serial Port Pins Before you can use the serial port, you must configure the associated port pins to serve as special- function signals.
Page 180 SERIAL I/O (SIO) PORT Address: 1F83H, 1F8BH SP x _CON (Continued) Reset State: x = 0–1 (8XC196MH) The serial port control (SP x _CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. 8XC196MH Function Number...
Page 181: Programming The Baud Rate And Clock Source
8XC196MC, MD, MH USER’S MANUAL 7.4.3 Programming the Baud Rate and Clock Source The SPx_BAUD register (Figure 7-7) selects the clock input for the baud-rate generator and de- fines the baud rate for all serial I/O modes. (For mode 4 with SCLKx# configured for input, the baud-rate generator is not used.) This register acts as a control register during write operations...
Page 182 SERIAL I/O (SIO) PORT Address: 1F84H, 1F8CH SP x _BAUD (Continued) Reset State: 0000H x = 0–1 (8XC196MH) The serial port baud rate x (SP x _BAUD) register selects the serial port x baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate.
Page 183: Enabling The Serial Port Interrupts
8XC196MC, MD, MH USER’S MANUAL CAUTION For mode 0 receptions, the BAUD_VALUE must be 0002H or greater. Otherwise, the resulting data in the receive shift register will be incorrect. The reason for this restriction is that the receive shift register is clocked from an internal signal rather than the signal on TXDx.
Page 184: Determining Serial Port Status
SERIAL I/O (SIO) PORT 7.4.5 Determining Serial Port Status You can read the SPx_STATUS register (Figure 7-8) to determine the status of the serial port. Reading SPx_STATUS clears all bits except TXE. For this reason, we recommend that you copy the contents of the SPx_STATUS register into a shadow register and then execute bit-test instruc- tions such as JBC and JBS on the shadow register.
Page 185 8XC196MC, MD, MH USER’S MANUAL The receiver checks for a valid stop bit. Unless a stop bit is found within the appropriate time, the framing error (FE) bit in the SPx_STATUS register is set. When the stop bit is detected, the data in the receive shift register is loaded into SBUFx_RX and the receive interrupt (RI) flag is set.
Page 186: Frequency Generator
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Page 188: Functional Overview
Appendix B, “Signal Descriptions.” For additional information and application examples, consult AP-483, Application Examples Using the 8XC196MC/MD Microcontroller (order number 272282). FUNCTIONAL OVERVIEW The frequency generator (Figure 8-1) has a frequency register, a count register, and an output sig- nal.
Page 189 8XC196MC, MD, MH USER’S MANUAL The frequency register (FREQ_GEN) controls the output frequency. The frequency generator loads the FREQ_GEN value into the counter. The counter counts down until it reaches zero, at which time the value is reloaded from the FREQ_GEN register. Each load toggles the D flip-flop, producing the 50% duty cycle output.
Page 190: Programming The Frequency Generator
FREQUENCY GENERATOR PROGRAMMING THE FREQUENCY GENERATOR This section explains how to configure the frequency generator and determine its status. 8.2.1 Configuring the Output The frequency generator’s output is multiplexed with P7.7, so you must configure it as a special- function output signal. To do so, follow this sequence: Clear bit 7 of P7_DIR.
Page 191: Determining The Current Value Of The Down-Counter
8XC196MC, MD, MH USER’S MANUAL 8.2.3 Determining the Current Value of the Down-counter You can read the FREQ_CNT register (Figure 8-3) to determine the current value of the down- counter. Address: 1FBAH FREQ_CNT Reset State: (8XC196MD) Read the frequency generator count (FREQ_CNT) register to determine the current value of the down-counter.
Page 192 FREQUENCY GENERATOR 8XC196 Device Output Signal Filter and Detector P7.7 A2704-02 Figure 8-4. Infrared Remote Control Application Block Diagram 40 kHz Zero = 2 ms One = 4 ms A2703-01 Figure 8-5. Data Encoding Example This program example was designed to run on an 8XC196MD demo board. It uses an EPA timer (timer 1) and compare channel (COMP3) to provide the timebase for the ones and zeros.
Page 193 8XC196MC, MD, MH USER’S MANUAL ; followed by a short (1 ms) pause, thus generating a MFM waveform. ; This program is assembled to run on the MD demo board. ;************************************** ; CONSTANT AND VARIABLE DECLARATIONS ;************************************** ; Program equates ;...
Page 194 FREQUENCY GENERATOR temp: temp1: temp2: buf_start: buf_cnt: bit_cnt: flag: ;bit 0 = zero being sent ;bit 1 = one being sent ;bit 5 = get next bit ;bit 6 = get next byte ;bit 7 = buffer send in progress xmit_buf: buf_size ;block of data to send...
Page 195 8XC196MC, MD, MH USER’S MANUAL temp,freq_gen[0] ;into freq gen ;enable interrupts ;***************************************** ; Now send buffer out as serial data bytes ;***************************************** ; This section issues a 1 millisecond pulse on P2.0 ; for use with an oscilloscope monitor. ;*****************************************...
Page 196 FREQUENCY GENERATOR cmpb buf_cnt,#0 ;see if last byte has been sent dec_buf_cnt ;no! ljmp all_done ;yes! dec_buf_cnt: decb buf_cnt ;decrement byte count get_bit: andb flag,#11011111b ;clear get bit flag shlb shift_reg,#1 ;shift MSB into carry flag send_one ;send a one ;else send zero send_zero: flag,#00000001b...
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Page 198: Waveform Generator
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Page 200: Waveform Generator Functional Overview
Appendix B, “Signal Descriptions.” For additional information and application examples, consult AP-483, Application Examples Using the 8XC196MC/MD Microcontroller (order number 272282). WAVEFORM GENERATOR FUNCTIONAL OVERVIEW The waveform generator (Figure 9-1) has three main parts: a timebase generator, phase driver channels, and control circuitry.
Page 201 8XC196MC, MD, MH USER’S MANUAL Timebase Generator WG_RELOAD Update WG_RELOAD WG_RELOAD Buffer WG_COUNTER = 1 Reload WG_COUNTER WG Interrupt Comparator WG_COUNTER = WG_RELOAD To Other Phase Driver Channels Phase Driver One of Three Channels P6.0 / WG1# Dead-time Phase &...
Page 202: Waveform Generator Signals And Registers
8XC196MH: The WG bit enables or disables the waveform generator interrupt. 8XC196MC, MD: The PI bit enables or disables the multiplexed peripheral interrupt. The corresponding bit in the PI_MASK register enables or disables the individual sources of the peripheral interrupt.
Page 203: Waveform Generator Operation
8XC196MC, MD, MH USER’S MANUAL Table 9-2. Waveform Generator Control and Status Registers (Continued) Mnemonic Address Description WG_CONTROL 1FCCH Waveform Generator Control The control register determines the waveform generator’s operating mode, starts and stops the counter, specifies the dead time for all phases, and indicates the current count direction.
Page 204: Phase Driver Channels
WAVEFORM GENERATOR 9.3.2 Phase Driver Channels The phase driver channels determine the duty cycle of the outputs. You specify the duty cycle by writing a value to each phase’s compare register (WG_COMPx). In all operating modes, the out- puts are initially asserted, and they remain asserted until the counter value (WG_COUNTER) matches the phase’s compare register (WG_COMPx) value.
Page 205: Register Buffering And Synchronization
The protection circuitry of the 8XC196MH operates in the same way as that of the 8XC196MC and 8XC196MD, but it allows you to choose the method used to disable the outputs. It can either place outputs in their inactive states, as the other devices do, or it can apply weak pull-ups to them.
Page 206: Operating Modes
WAVEFORM GENERATOR The WG_RELOAD register is updated when the counter value reaches the reload value. The WG_COUNTER register is loaded with the updated WG_RELOAD value, so a new reload value takes effect for the next cycle. In mode 3 (and mode 4 for the 8XC196MH), the WG_RELOAD register can be updated when an EPA event occurs.
Page 207 8XC196MC, MD, MH USER’S MANUAL Table 9-3. Operation in Center-aligned and Edge-aligned Modes Step Center-aligned Modes Edge-aligned Modes Load WG_COUNTER with WG_RELOAD. Load WG_COUNTER with 0001H. Leave outputs deasserted. Leave outputs deasserted. When counter is enabled, begin counting down. When counter is enabled, begin counting up.
Page 208: Center-Aligned Modes
WAVEFORM GENERATOR 9.3.5.1 Center-aligned Modes In the center-aligned modes, the counter counts down from the WG_RELOAD value to 1, then counts back up from 1 to WG_RELOAD. When you write to the WG_RELOAD register, WG_COUNTER is loaded with the reload value. When you set the enable bit in the control reg- ister, the counter begins counting down and continues counting until it reaches 1, waits one state time, and starts counting up until it reaches WG_RELOAD.
Page 209: Edge-Aligned Modes
8XC196MC, MD, MH USER’S MANUAL WG_COMP x WG_COUNTER WG_COUNTER =WG_COMP x WG Interrupt P6.0 / WG1# Note: Carrier period and duty cycle both change since WG_COMP is not changed. P6.1 / WG1 Mode 0, OP0 = OP1 = 1, PH1.0 = PH1.1 = PH1.2 = 1 = Additional interrupt in mode 1 only.
Page 210 WAVEFORM GENERATOR WG_RELOAD EPA Event WG_RELOAD Updated (Mode 3 Only) Value Counter Enabled WG_COUNTER Value Carrier Period Reset Write to WG_RELOAD A2639-01 Figure 9-6. Edge-aligned Modes — Counter Operation EPA Event WG_COMP x WG_COUNTER Carrier WG_COUNTER Period =WG_COMP WG Interrupt P6.0 / WG1# Note: Carrier period and duty cycle both...
Page 211: Programming The Waveform Generator
8XC196MC, MD, MH USER’S MANUAL PROGRAMMING THE WAVEFORM GENERATOR This section explains how to configure the waveform generator and determine its status. 9.4.1 Configuring the Outputs The waveform generator’s outputs are multiplexed with general-purpose output port 6, so you must configure them as special-function signals to use them as waveform-generator outputs. The WG_OUTPUT register (Figure 9-8) configures the pins, establishes the output polarity, and con- trols whether changes to the outputs are synchronized with an event or take effect immediately.
Page 212 WAVEFORM GENERATOR Address: 1FC0H WG_OUTPUT (Waveform Generator) Reset State: 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6. Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT.
Page 213 8XC196MC, MD, MH USER’S MANUAL Address: 1FC0H WG_OUTPUT (Waveform Generator) (Continued) Reset State: 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6.
Page 214: Controlling The Protection Circuitry And Extint Interrupt Generation
This bit enables and disables the outputs. 0 = disable outputs 1 = enable outputs † On the 8XC196MC, MD devices, this bit is reserved. For compatibility with future devices, always write as zero. Figure 9-9. Waveform Generator Protection (WG_PROTECT) Register 9-15...
Page 215: Specifying The Carrier Period And Duty Cycle
8XC196MC, MD, MH USER’S MANUAL 9.4.3 Specifying the Carrier Period and Duty Cycle The reload register (WG_RELOAD) and the phase compare registers (WG_COMPx) control the carrier period and duty cycle. Write a value to the reload register (Figure 9-10) to establish the carrier period.
Page 216: Specifying The Operating Mode And Dead Time And Starting The Counter
WAVEFORM GENERATOR Address: 1FC2H,1FC4H,1FC6H WG_COMP x Reset State: 0000H x = 1–3 The phase compare (WG_COMP x ) register controls the duty cycle of each phase. Write a value to each phase compare register to specify the length of time that the associated outputs will remain asserted.
Page 217 8XC196MC, MD, MH USER’S MANUAL Address: 1FCCH WG_CONTROL Reset State (MC, MD): 00C0H Reset State (MH): 8000H The waveform generator control (WG_CONTROL) register controls the operating mode, dead time, and count direction, and enables and disables the counter. — Function...
Page 218: Determining The Waveform Generator's Status
WAVEFORM GENERATOR DETERMINING THE WAVEFORM GENERATOR’S STATUS Read WG_CONTROL (Figure 9-12 on page 9-18) to determine the current dead-time value, counter status, count direction, and operating mode. Read WG_COUNTER (Figure 9-13) to de- termine the current counter value. Address: 1FCAH WG_COUNTER Reset State (MC, MD): XXXXH...
Page 219: Design Considerations
8XC196MC, MD, MH USER’S MANUAL To enable the interrupts, set the corresponding mask bits in the mask register (see Table 9-2 on page 9-3) and execute the EI instruction to enable interrupt servicing. You can read the interrupt pending register to determine whether there are any pending interrupts. Refer to Chapter 5, “Stan- dard and PTS Interrupts”...
Page 220: Extint Interrupts And Protection Circuitry
PROGRAMMING EXAMPLE This example was designed to run on an 8XC196MC demo board, but it can easily be modified for an evaluation board. The program allows you to test the waveform generator’s registers and observe their effects on the output waveforms. All variables are defined as words and are masked to the appropriate length before they are written to the registers.
Page 221 8XC196MC, MD, MH USER’S MANUAL ph3: dsw 1 ;P6.4,5 config dsw 1 ;0=disable output, 1=enable output dsw 1 ;0=enable protection, 1=disable dsw 1 ;0=falling edge trig, 1=rising edge dsw 1 ;0=edge, 1=sample dsw 1 ;0=stop cntr, 1=start dead: dsw 1 ;10-bit dead time...
Page 222 WAVEFORM GENERATOR ;load WFG registers call wgout ;initialize WG_OUTPUT register call loadregs ;initialize reload & compare regs call protect ;initialize protection call wgcon ;initialize WG_CONTROL ;enable interrupts & loop here sjmp $ ;**************************************** ; form WG_OUTPUT value from variable data ;**************************************** wgout: temp,op1...
Page 223 8XC196MC, MD, MH USER’S MANUAL temp1,temp ;combine temp,p6 ;get p6 bit temp,#0001h ;mask temp,#6 ;move to correct location temp1,temp ;combine temp,ph3 ;get ph3 bits again temp,#0003h ;mask for ph3.0 & 1 temp,#4h ;move temp1,temp ;combine1 temp,ph2 ;get ph2 bits again temp,#0003h ;mask for ph2.0 &...
Page 224 WAVEFORM GENERATOR temp,#0001h ;mask temp,#3 ;shift to correct location temp1,it ;interrupt type bit temp1,#0001h ;mask temp1,#2 ;shift to correct location temp,temp1 ;combine into temp temp1,dp ;disable protection bit temp1,#0001h ;mask temp1,#1 ;shift to correct location temp,temp1 ;combine into temp temp1,eo ;enable output bit temp1,#0001h ;mask...
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Page 226: Pulse-Width Modulator
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Page 228: Pwm Functional Overview
CHAPTER 10 PULSE-WIDTH MODULATOR The pulse-width modulator (PWM) module has two output pins, each of which can output a PWM signal with a fixed, programmable frequency and a variable duty cycle. These outputs can be used to drive motors that require an unfiltered PWM waveform for optimal efficiency, or they can be filtered to produce a smooth analog signal.
Page 229: Pwm Signals And Registers
8XC196MC, MD, MH USER’S MANUAL PWM x _CONTROL Load Buffer Buffer x Comparator x RS Flip-flop x Port 6 Control WG_OUT Internal Down Counter PWM x P6.x/PWM x Clock Output PWM_COUNT Count Signal = 00H PWM_PERIOD Load Shared Circuitry A2761-02 Figure 10-1.
Page 230: Pwm Operation
PULSE-WIDTH MODULATOR Table 10-2. PWM Control and Status Registers Mnemonic Address Description PWM0_CONTROL 1FB0H PWM Duty Cycle PWM1_CONTROL 1FB2H This register controls the PWM duty cycle. A zero loaded into this register will cause the PWM to output a low continuously (0% duty cycle).
Page 231: Programming The Frequency And Period
8XC196MC, MD, MH USER’S MANUAL The counter counts down to 00H, at which time the PWM output is driven high, the counter value is reloaded from the PWM_PERIOD register, and the contents of the control registers are loaded into the buffers. The PWM output remains high until the counter value matches the value in the buffer, at which time the output is pulled low.
Page 232 PULSE-WIDTH MODULATOR where: PWM_PERIOD = 8-bit value to load into the PWM_PERIOD register = input frequency on XTAL1 pin, in MHz XTAL = output period on the PWM output pins, in µs = output frequency on the PWM output pins, in MHz Table 10-3.
Page 233: Programming The Duty Cycle
8XC196MC, MD, MH USER’S MANUAL Address: 1FB4H PWM_PERIOD Reset State: The PWM period (PWM_PERIOD) register controls the period of the PWM outputs. It contains a value that determines the number of state counts necessary for incrementing the PWM counter. The value of PWM_PERIOD is loaded into the PWM period count register whenever the count equals zero.
Page 234: Sample Calculations
PULSE-WIDTH MODULATOR Address: Table 10-2 on page PWM x _CONTROL 10-3 x = 0–1 Reset State: The PWM control (PWM x _CONTROL) register determines the duty cycle of the PWM x channel. A zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in this register causes the PWM to have its maximum duty cycle (99.6% duty cycle).
Page 235: Enabling The Pwm Outputs
8XC196MC, MD, MH USER’S MANUAL Address: 1FB6H PWM_COUNT Reset State: (read only) The PWM count (PWM_COUNT) register provides the current value of the decremented period counter. PWM Count Value Function Number PWM Count Value This register contains the current value of the decremented period counter.
Page 236 PULSE-WIDTH MODULATOR Address: 1FC0H WG_OUTPUT (Waveform Generator) Reset State: 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6. Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT.
Page 237: Generating Analog Outputs
8XC196MC, MD, MH USER’S MANUAL 10.5.4 Generating Analog Outputs PWM modules can generate a rectangular pulse train that varies in duty cycle and period. Filter- ing this output will create a smooth analog signal. To make a signal swing over the desired analog range, first buffer the signal and then filter it with either a simple RC network or an active filter.
Page 238: Event Processor Array (Epa)
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Page 240: Epa Functional Overview
Each input capture or an output compare sets an interrupt pending bit. This bit can optionally cause an interrupt. Table 11-1 lists the capture/compare and compare-only channels for each de- vice in the 8XC196Mx family. Table 11-1. EPA Channels Device Capture/Compare Channels Compare-only Channels 8XC196MC EPA3:0 COMP3:0 8XC196MD EPA5:0 COMP5:0 8XC196MH...
Page 241: Epa And Timer/Counter Signals And Registers
COMP y Interrupt Compare-only COMP y Channel y Notes: For the 8XC196MC, x & y = 3. For the 8XC196MD, x & y = 5. For the 8XC196MH, x = 1 & y = 3. A2846-01 Figure 11-1. EPA Block Diagram 11.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS...
Page 242 EVENT PROCESSOR ARRAY (EPA) Table 11-2. EPA and Timer/Counter Signals (Continued) Port Pin Signal Description Signals 8XC196MC 8XC196MD 8XC196MH Type P2.4 P2.4 P2.4 COMP0 Output of the compare-only channels. P2.5 P2.5 P2.5 COMP1 P2.6 P2.6 P2.6 COMP2 P2.7 P2.7 P2.3 COMP3 —...
Page 243 8XC196MC, MD, MH USER’S MANUAL Table 11-3. EPA Control and Status Registers (Continued) Address Mnemonic Description INT_PEND 0009H 0009H 0009H Interrupt Pending Any set bit in this 8-bit register indicates a pending interrupt request. INT_PEND1 0012H 0012H 0012H Interrupt Pending 1 Any set bit in this 8-bit register indicates a pending interrupt request.
Page 244: Timer/Counter Functional Overview
EVENT PROCESSOR ARRAY (EPA) Table 11-3. EPA Control and Status Registers (Continued) Address Mnemonic Description PI_MASK 1FBCH 1FBCH 1FBCH Peripheral Interrupt Mask The bits in this register enable and disable (mask) the timer 1 and 2 overflow/underflow interrupt requests, the waveform generator interrupt request (MC, MD), the EPA compare-only channel 5 interrupt request ( MD), and the serial port error interrupts (MH).
Page 245 8XC196MC, MD, MH USER’S MANUAL T2CONTROL.2:0 Timer 2 Prescaler XTAL1 Module Clock Overflow/ Timer 1 Overflow/Underflow Underflow TIMER2 T2CONTROL.6 OVRTM Direction Interrupt T1CONTROL.2:0 Timer 1 XTAL1 Prescaler Module Clock T1CLK Overflow/ Underflow Quadrature Count T1RELOAD TIMER1 T1DIR Direction T1CONTROL.6 Quadrature Direction A3131-01 Figure 11-2.
Page 246: Cascade Mode (Timer 2 Only)
EVENT PROCESSOR ARRAY (EPA) where: prescaler_divisor is the clock prescaler divisor from the T x CONTROL registers (see “Timer 1 Control (T1CONTROL) Register” on page 11-16 and “Timer 2 Control (T2CONTROL) Register” on page 11-17). is the input frequency on XTAL1. XTAL 11.3.1 Cascade Mode (Timer 2 Only) Timer 2 can be used in cascade mode.
Page 247 8XC196MC, MD, MH USER’S MANUAL Increment ® 96 Microcontroller Decrement T1CLK X_internal Optical Reader T1DIR Y_internal A1550-01 Figure 11-3. Quadrature Mode Interface Table 11-4. Quadrature Mode Truth Table State of X_internal State of Y_internal Count Direction (T1CLK) (T1DIR) ↑ Increment ↓...
Page 248: Epa Channel Functional Overview
+ 4 x + 3 x + 2 x + 1 † CLKOUT is available on the 8XC196MC and 8XC196MD only. A1549-01 Figure 11-4. Quadrature Mode Timing and Count 11.4 EPA CHANNEL FUNCTIONAL OVERVIEW The EPA has both programmable capture/compare and compare-only channels. Each cap- ture/compare channel can perform the following tasks.
Page 249: Operating In Capture Mode
8XC196MC, MD, MH USER’S MANUAL Each EPA channel has a control register, EPAx_CON (capture/compare channels) or COMPx_CON (compare-only channels); an event-time register, EPAx_TIME (capture/compare channels) or COMPx_TIME (compare-only channels); and a timer input (Figure 11-5). The con- trol register selects the timer, the mode, and either the event to be captured or the event that is to occur.
Page 250 EVENT PROCESSOR ARRAY (EPA) TIMER x Event Occurs at EPA Pin Capture Buffer Interrupt Pending Bit EPA x _TIME Read-out Time Value A2458-02 Figure 11-6. EPA Simplified Input-capture Structure If a third event occurs before the CPU reads the event-time register, the overwrite bit (EPAx_CON.0) determines how the EPA will handle the event.
Page 251: Epa Overruns
8XC196MC, MD, MH USER’S MANUAL Table 11-5. Action Taken When a Valid Edge Occurs Status of Overwrite Bit Capture Buffer Action Taken When a Valid Edge Occurs (EPA x _CON.0) & EPA x _TIME empty Edge is captured and event time is loaded into the capture buffer and EPA x _TIME register.
Page 252: Preventing Epa Overruns
EVENT PROCESSOR ARRAY (EPA) 11.4.1.2 Preventing EPA Overruns Any one of the following methods can be used to prevent or recover from an EPA overrun situa- tion. • Clear EPAx_CON.0 When the overwrite bit (EPAx_CON.0) is zero, the EPA does not consider the captured edge until the EPAx_TIME register is read and the data in the capture buffer is transferred to EPAx_TIME.
Page 253: Generating The Highest-Speed Pwm Output
8XC196MC, MD, MH USER’S MANUAL The maximum output frequency depends upon the total interrupt latency and the interrupt-service execution times used by your system. As additional EPA channels and the other functions of the microcontroller are used, the maximum PWM frequency decreases because the total interrupt la- tency and interrupt-service execution time increases.
Page 254: Programming The Epa And Timer/Counters
EVENT PROCESSOR ARRAY (EPA) With this method, the resolution of the EPA (selected by the TxCONTROL registers; see Figure 11-8 on page 11-16 and Figure 11-9 on page 11-17) determines the maximum PWM output fre- quency. (Resolution is the minimum time required between consecutive captures or compares.) When the input frequency on XTAL1 is 16 MHz, a 250 ns resolution results in a maximum PWM of 4 MHz.
Page 255 8XC196MC, MD, MH USER’S MANUAL Address: 1F78H T1CONTROL Reset State: The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 256 EVENT PROCESSOR ARRAY (EPA) Address: 1F7CH T2CONTROL Reset State: The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 257: Programming The Capture/Compare Channels
8XC196MC, MD, MH USER’S MANUAL 11.5.3 Programming the Capture/Compare Channels The EPAx_CON register controls the function of its assigned capture/compare channel. The reg- isters are identical with the exception of bit 2. For EPA channels 0, 2, and 4, setting this bit enables an EPA event to cause a waveform generator reload.
Page 258 See Table 11-3 on page 11-3 EPA x _CON Reset State: x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels. x = 0, 2, 4...
Page 259 8XC196MC, MD, MH USER’S MANUAL Address: See Table 11-3 on page 11-3 EPA x _CON (Continued) Reset State: x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 260 See Table 11-3 on page 11-3 EPA x _CON (Continued) Reset State: x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels. x = 0, 2, 4...
Page 261: Programming The Compare-Only Channels
8XC196MC, MD, MH USER’S MANUAL 11.5.4 Programming the Compare-only Channels To program a compare event, you must first write to the COMPx_CON register (Figure 11-11) to configure the compare-only channel and then load the event time into COMPx_TIME. COMPx_CON has the same bits and settings as EPAx_CON. COMPx_TIME is functionally iden- tical to EPAx_TIME.
Page 262: Enabling The Epa Interrupts
EVENT PROCESSOR ARRAY (EPA) See Table 11-3 on COMP x _CON (Continued) Address: page 11-3 x = 0–3 (8XC196MC, MH) x = 0–5 (8XC196MD) Reset State: The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels.
Page 263: Determining Event Status
8XC196MC, MD, MH USER’S MANUAL 11.7 DETERMINING EVENT STATUS In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event (even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt pending bit is set each time a programmed event is captured and the event time moves from the capture buffer to the EPAx_TIME register.
Page 264: Analog-To-Digital (A/D) Converter
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Page 266: A/D Converter Functional Overview
CHAPTER 12 ANALOG-TO-DIGITAL (A/D) CONVERTER The analog-to-digital (A/D) converter can convert an analog input voltage to a digital value and set the A/D interrupt pending bit when it stores the result. It can also monitor a pin and set the A/D interrupt pending bit when the input voltage crosses over or under a programmed threshold voltage.
Page 267: A/D Converter Signals And Registers
8XC196MC, MD, MH USER’S MANUAL 12.2 A/D CONVERTER SIGNALS AND REGISTERS Table 12-1 lists the A/D signals and Table 12-2 describes the control and status registers. Al- though the analog inputs are multiplexed with I/O port pins, no configuration is necessary.
Page 268: A/D Converter Operation
ANALOG-TO-DIGITAL (A/D) CONVERTER Table 12-2. A/D Control and Status Registers (Continued) Mnemonic Address Description P0_PIN 1FA8H (MC, MD) Port 0 Pin State 1FDAH (MH) Read P0_PIN to determine the current values of the port 0 pins. Reading the port induces noise into the A/D converter, decreasing the accuracy of any conversion in progress.
Page 269: Programming The A/D Converter
8XC196MC, MD, MH USER’S MANUAL Once the A/D converter receives the command to start a conversion, a delay time elapses before sampling begins. (EPA-initiated conversions begin after the capture/compare event. Immediate conversions, those initiated directly by a write to AD_COMMAND, begin within three state times after the instruction is completed.) During this sample delay, the hardware clears the suc-...
Page 270: Programming The A/D Test Register
ANALOG-TO-DIGITAL (A/D) CONVERTER 12.4.1 Programming the A/D Test Register The AD_TEST register (Figure 12-2) analog specifies an offset voltage to be applied to the resis- tor ladder. To use the zero-offset adjustment, first perform two conversions, one on ANGND and one on V .
Page 271: Programming The A/D Time Register
8XC196MC, MD, MH USER’S MANUAL Address: 1FAAH AD_RESULT (Write) Reset State (MC, MD): FFC0H Reset State (MH): 7FC0H The high byte of the A/D result (AD_RESULT) register can be written to set the reference voltage for the A/D threshold-detection modes.
Page 272: Programming The A/D Command Register
ANALOG-TO-DIGITAL (A/D) CONVERTER Address: 1FAFH AD_TIME Reset State: The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit. This register programs the speed at which the A/D can run — not the speed at which it can convert correctly.
Page 273: Enabling The A/D Interrupt
8XC196MC, MD, MH USER’S MANUAL Address: 1FACH AD_COMMAND Reset State: The A/D command (AD_COMMAND) register selects the A/D channel number to be converted, controls whether the A/D converter starts immediately or with an EPA command, and selects the conversion mode.
Page 274: Determining A/D Status And Conversion Results
ANALOG-TO-DIGITAL (A/D) CONVERTER 12.5 DETERMINING A/D STATUS AND CONVERSION RESULTS You can read the AD_RESULT register (Figure 12-6) to determine the status of the A/D convert- er. The AD_RESULT register is cleared when a new conversion is started; therefore, to prevent losing data, you must read both bytes before a new conversion starts.
Page 275: Design Considerations
8XC196MC, MD, MH USER’S MANUAL 12.6 DESIGN CONSIDERATIONS This section describes considerations for the external interface circuitry and describes the errors that can occur in any A/D converter. The datasheet lists the absolute error specification, which includes all deviations between the actual conversion process and an ideal converter. However, because the various components of error are important in many applications, the datasheet also lists the specific error components.
Page 276: Minimizing The Effect Of High Input Source Resistance
ANALOG-TO-DIGITAL (A/D) CONVERTER Typically, the (R + 1) term is the major contributor to the total resistance and the factor that determines the minimum sample time specified in the datasheet. 12.6.1.1 Minimizing the Effect of High Input Source Resistance Under some conditions, the input source resistance (R ) can be great enough to affect the SOURCE measurement.
Page 277: Suggested A/D Input Circuit
8XC196MC, MD, MH USER’S MANUAL 12.6.1.2 Suggested A/D Input Circuit The suggested A/D input circuit shown in Figure 12-8 provides limited protection against over- voltage conditions on the analog input. Should the input voltage be driven significantly below ANGND or above V , diode D2 or D1 will forward bias at about 0.8 volts.
Page 278: Using Mixed Analog And Digital Inputs
ANALOG-TO-DIGITAL (A/D) CONVERTER ANGND should be within about ± 50 mV of V should be well regulated and used only for the A/D converter. The V supply can be between 4.5 and 5.5 volts and must be able to source approximately 5 mA (see the datasheet for actual specifications). V should be approx- imately the same voltage as V and V...
Page 279 8XC196MC, MD, MH USER’S MANUAL In many applications, it is less critical to record the absolute accuracy of an input than it is to de- tect that a change has occurred. This approach is acceptable as long as the converter is monotonic and has no missing codes.
Page 280 ANALOG-TO-DIGITAL (A/D) CONVERTER FINAL CODE TRANSITION OCCURS WHEN THE APPLIED VOLTAGE IS EQUAL TO (Vref – 1.5 (LSB)). ACTUAL CHARACTERISTIC OF AN IDEAL A/D CONVERTER THE VOLTAGE CHANGE BETWEEN THE ADJACENT CODE TRANSITIONS (THE “CODE WIDTH”) IS = 1 LSB. FIRST CODE TRANSITION OCCURS WHEN THE APPLIED VOLTAGE IS EQUAL TO 1/2 LSB.
Page 281 8XC196MC, MD, MH USER’S MANUAL FULL SCALE ERROR IDEAL CHARACTERISTIC ABSOLUTE ERROR ACTUAL CHARACTERISTIC ZERO OFFSET 6 1/2 INPUT VOLTAGE (LSBs) A0084-01 Figure 12-10. Actual and Ideal A/D Conversion Characteristics The actual characteristic of a hypothetical 3-bit converter is not perfect. When the ideal charac- teristic is overlaid with the actual characteristic, the actual converter is seen to exhibit errors in the locations of the first and final code transitions and in code widths, as shown in Figure 12-10.
Page 282 ANALOG-TO-DIGITAL (A/D) CONVERTER Differential nonlinearity is the degree to which actual code widths differ from the ideal one-LSB width. It provides a measure of how much the input voltage may have changed in order to produce a one-count change in the conversion result. In the 10-bit converter, the code widths are ideally 5 mV (V / 1024).
Page 283 8XC196MC, MD, MH USER’S MANUAL IDEAL FULL-SCALE CODE TRANSITION IDEAL STRAIGHT LINE TRANSFER FUNCTION ACTUAL FULL-SCALE CODE TRANSITION DIFFERENTIAL TERMINAL BASED NON-LINEARITY CHARACTERISTIC (POSITIVE) (corrected for zero-offset and full-scale error) IDEAL CODE WIDTH ACTUAL CHARACTERISTIC NON-LINEARITY DIFFERENTIAL NON-LINEARITY (NEGATIVE) IDEAL CODE WIDTH...
Page 284: Minimum Hardware Considerations
Minimum Hardware Considerations Get other manuals https://www.bkmanuals.com...
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Page 286: Minimum Connections
Reference Voltage for the A/D Converter This pin also supplies operating voltage to both the analog portion of the A/D converter and the logic used to read port 0 (also port 1 in the 8XC196MC and 8XC196MD). Digital Circuit Ground Connect each V pin to ground through the lowest possible impedance path.
Page 287: Unused Inputs
8XC196MC, MD, MH USER’S MANUAL Table 13-1. Minimum Required Signals (Continued) Signal Type Description Name XTAL1 Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal (MC/MD only).
Page 288 MINIMUM HARDWARE CONSIDERATIONS (Note 1) 20 pF 20 pF XTAL2 XTAL1 RESET# (Note 2) 0.01 µF 4.7 µF BUSWIDTH (Note 3) READY 1 µF 1 µF BHE# ANGND Port 5 / Bus Control (Note 4) Input-only INST Port Pins (Note 5) 8XC196 Device Notes: 1.
Page 289: Applying And Removing Power
8XC196MC, MD, MH USER’S MANUAL 13.2 APPLYING AND REMOVING POWER When power is first applied to the device, RESET# must remain continuously low for at least one state time after the power supply is within tolerance and the oscillator/clock has stabilized; oth- erwise, operation might be unpredictable.
Page 290: The On-Chip Oscillator Circuitry
A/D conversions. Even if the A/D converter will not be used, V and ANGND must be connected to provide power to port 0. On the 8XC196MC and MD, they also provide power to port 1. Refer to “Analog Ground and Reference Voltages” on page 12-12 for a detailed discussion of A/D power and ground recommendations.
Page 291 8XC196MC, MD, MH USER’S MANUAL Figure 13-4 shows the connections between the external crystal and the device. When designing an external oscillator circuit, consider the effects of parasitic board capacitance, extended oper- ating temperatures, and crystal specifications. Consult the manufacturer’s datasheet for perfor- mance specifications and required capacitor values.
Page 292: Using An External Clock Source
MINIMUM HARDWARE CONSIDERATIONS 13.5 USING AN EXTERNAL CLOCK SOURCE To use an external clock source, apply a clock signal to XTAL1 and let XTAL2 float (Figure 13-5). To ensure proper operation, the external clock source must meet the minimum high and low times (T and T ) and the maximum rise and fall transition times (T...
Page 293: Resetting The Device
(Tables in Appendix B list the reset states of the pins (see Table B-8 on page B-23 for the 8XC196MC and 8XC196MD or Table B-9 on page B-25 for the 8XC196MH). See Table C-2 on page C-2 for the reset values of the SFRs.) The device remains in its reset state until RESET# is deasserted.
Page 294 MINIMUM HARDWARE CONSIDERATIONS The 8XC196MH provides the option of an internal-only reset or an internal reset that is also re- flected externally (by the RESET# pin). The GEN_CON register controls whether an internal re- set asserts the external RESET# signal and indicates the source of the most recent reset. Figure 13-8 describes the general configuration register, GEN_CON.
Page 295: Generating An External Reset
8XC196MC, MD, MH USER’S MANUAL Internal External V CC Clock Reset State Internal Machine Reset † R RST Trigger Signal Count Complete RESET# ~200 Ω GEN_CON.0 (MH Only) RST Instruction WDT Overflow IDLPD Invalid Key † See the datasheet for minimum and maximum R values.
Page 296 MINIMUM HARDWARE CONSIDERATIONS RESET# 4.7 µF MCS ® 96 Microcontroller A0276-02 Figure 13-10. Minimum Reset Circuit Other devices in the system may not be reset because the capacitor will keep the voltage above . Since RESET# is asserted for only 16 state times, it may be necessary to lengthen and buffer the system-reset pulse.
Page 297: Issuing The Reset (Rst) Instruction
Once the watchdog is activated, only a reset can disable it. The 8XC196MC and 8XC196MD allow only one reset interval, 64K state times. This requires your software to interrupt itself every 65,535 state times to reset the watchdog. The 8XC196MH allows you to choose a longer interval.
Page 298 You must write two consecutive bytes to the watchdog register (location 0AH) to clear it. For the 8XC196MC and MD, the first byte must be 1EH and the second must be E1H. For the 8XC196MH, the first byte must also be 1EH; however, the second byte can be one of four values.
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Page 300: Special Operating Modes
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Page 302: Special Operating Mode Signals And Registers
CHAPTER 14 SPECIAL OPERATING MODES The 8XC196MC, MD, and MH provide two power saving modes: idle and powerdown. They also provide an on-circuit emulation (ONCE) mode that electrically isolates the device from the other system components. This chapter describes each mode and explains how to enter and exit each.
Page 303 8XC196MC, MD, MH USER’S MANUAL Table 14-1. Operating Mode Control Signals (Continued) Signal Port Pin Type Description Name P5.4 ONCE# On-circuit Emulation Holding ONCE# low during the rising edge of RESET# places the device into on-circuit emulation (ONCE) mode. This mode puts all pins, except XTAL1 and XTAL2, into a high-impedance state, thereby isolating the device from other components in the system.
Page 304: Reducing Power Consumption
SPECIAL OPERATING MODES Table 14-2. Operating Mode Control and Status Registers (Continued) Mnemonic Address Description P1_DIR (MH) 1F9BH Port x Direction P2_DIR 1FD2H Each bit of P x _DIR controls the direction of the corresponding pin. P5_DIR 1FF3H Clearing a bit configures a pin as a complementary output; setting P7_DIR (MD) 1FD3H a bit configures a pin as an input or open-drain output.
Page 305: Idle Mode
(SFRs) and register RAM retain their data and the peripherals and interrupt system remain active. Tables in Appendix B list the values of the pins during idle mode (see Table B-8 on page B-23 for the 8XC196MC and 8XC196MD or Table B-9 on page B-25 for the 8XC196MH). 14-4...
Page 306: Powerdown Mode
Tables in Appendix B list the values of the pins during powerdown mode (see Table B-8 on page B-23 for the 8XC196MC and 8XC196MD or Table B-9 on page B-25 for the 8XC196MH). If V is maintained above the minimum specification, the special-function regis- ters (SFRs) and register RAM retain their data.
Page 307: Entering Powerdown Mode
8XC196MC, MD, MH USER’S MANUAL 14.4.2 Entering Powerdown Mode Before entering powerdown, complete the following tasks: • Complete all serial port transmissions or receptions. Otherwise, when the device exits powerdown, the serial port activity will continue where it left off and incorrect data may be transmitted or received.
Page 308: Asserting The External Interrupt Signal
SPECIAL OPERATING MODES 14.4.3.3 Asserting the External Interrupt Signal The final way to exit powerdown mode is to assert the external interrupt signal (EXTINT) for at least 50 ns. Although EXTINT is normally a sampled input, the powerdown circuitry uses it as a level-sensitive input.
Page 309: Selecting R And C
8XC196MC, MD, MH USER’S MANUAL V CC 8XC196 Device R 1 1 MΩ Typical V PP C 1 1µF Typical A0279-01 Figure 14-3. External RC Circuit During normal operation (before entering powerdown mode), an internal pull-up holds the pin at V .
Page 310 SPECIAL OPERATING MODES EXTINT 200 µA C 1 Discharge R 1 x C 1 Recovery V PP , Volts Time Constant Pullup On Code Execution Resumes Time, ms A0151-01 Figure 14-4. Typical Voltage on the V Pin While Exiting Powerdown Select a resistor that will not interfere with the discharge current.
Page 311: Once Mode
8XC196MC, MD, MH USER’S MANUAL When selecting the capacitor, determine the worst-case discharge time needed for the oscillator to stabilize, then use this formula to calculate an appropriate value for C × ------------------- - where: is the capacitor value, in farads...
Page 312: Reserved Test Modes
Normal operations resume when RESET# goes high. 14.6 RESERVED TEST MODES A special test-mode-entry pin (P2.6) is provided for Intel’s in-house testing only. These test modes can be entered accidentally if you configure the test-mode-entry pin as an input and hold it low during the rising edge of RESET#.
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Page 314: Interfacing With External Memory
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Page 316: External Memory Interface Signals And Registers
CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY The microcontroller can interface with a variety of external memory devices. It supports either a fixed 8-bit data bus width, a fixed 16-bit data bus width, or a dynamic 8-bit/16-bit data bus width; internal control of wait states for slow external memory devices; and several bus-control modes. These features provide a great deal of flexibility when interfacing with external memory systems.
Page 317 8XC196MC, MD, MH USER’S MANUAL Table 15-1. External Memory Interface Signals (Continued) Signal Port Pin Type Description Name P5.0 Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus.
Page 318 INTERFACING WITH EXTERNAL MEMORY Table 15-1. External Memory Interface Signals (Continued) Signal Port Pin Type Description Name — External Access This input determines whether memory accesses to special-purpose and program memory partitions are directed to internal or external memory. (See Table 4-1 on page 4-2 for address ranges of special- purpose and program memory partitions.) These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low.
Page 319 8XC196MC, MD, MH USER’S MANUAL Table 15-1. External Memory Interface Signals (Continued) Signal Port Pin Type Description Name † WRH# P5.5 Write High During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations.
Page 320: Chip Configuration Registers And Chip Configuration Bytes
INTERFACING WITH EXTERNAL MEMORY Table 15-2. External Memory Interface Registers (Continued) Register Address Description Mnemonic P5_REG 1FF5H Port 5 Data Output For an input, regardless of the pin’s configuration, set the corresponding P5_REG bit. For an output, write the data to be driven out by each pin to the corre- sponding bit of P5_REG.
Page 321 8XC196MC, MD, MH USER’S MANUAL When the microcontroller returns from reset, the bus controller fetches the CCBs and loads them into the CCRs. From this point, these CCR bit values define the chip configuration until the mi- crocontroller is reset again. The CCR bits are described in Figures 15-1 and 15-2. (Refer to Chap- ter 16, “Programming the Nonvolatile Memory,”...
Page 322 INTERFACING WITH EXTERNAL MEMORY no direct access† CCR0 The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width. LOC1 LOC0 IRC1...
Page 323 8XC196MC, MD, MH USER’S MANUAL no direct access† CCR0 (Continued) The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
Page 324 INTERFACING WITH EXTERNAL MEMORY † no direct access CCR1 The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. IRC2 Function Number...
Page 325: Bus Width And Multiplexing
8XC196MC, MD, MH USER’S MANUAL † no direct access CCR1 (Continued) The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width.
Page 326 INTERFACING WITH EXTERNAL MEMORY Bus Control Bus Control 8-bit Address 16-bit Multiplexed High Address/Data AD15:8 AD15:0 (Port 4) (Ports 4 and 3) 8-bit Multiplexed Address/Data AD7:0 (Port 3) 8XC196 8XC196 16-bit Bus 8-bit Bus A3068-01 Figure 15-3. Multiplexing and Bus Width Options After reset, but before the CCB fetch, the microcontroller is configured for 8-bit bus mode, re- gardless of the BUSWIDTH input.
Page 327 XTAL1 † CLKOUT (min) CLGX BUSWIDTH Valid AVGV AD15:0 Data In Address Out † The CLKOUT pin is available only on the 8XC196MC, MD. A3162-01 Figure 15-4. BUSWIDTH Timing Diagram (8XC196MC, MD) XTAL1 XTAL1 AVGV BUSWIDTH LLGV (max) LLGX (min)
Page 328: Timing Requirements For Buswidth
All AC timings are referenced to T XTAL † This specification applies to the 8XC196MC, MD microcontrollers only. †† This specification applies to the 8XC196MH microcontroller only. The BUSWIDTH signal can be used in numerous applications. For example, a system could store code in a 16-bit memory device and data in an 8-bit memory device.
Page 329: 16-Bit Bus Timings
8XC196MC, MD, MH USER’S MANUAL 15.3.2 16-bit Bus Timings When the microcontroller is configured to operate in the 16-bit bus-width mode, lines AD15:0 form a 16-bit multiplexed address/data bus. Figure 15-6 shows an idealized timing diagram for the external read and write cycles. Comprehensive timing specifications are shown in Figure 15-22 on page 15-32.
Page 330 CLKOUT Valid BUSWIDTH AD15:0 Address Out Data In (read) INST Valid AD15:0 Address Out Data Out (write) † The CLKOUT pin is available only on the 8XC196MC, MD. A3163-01 Figure 15-6. Timings for 16-bit Buses 15-15 Get other manuals https://www.bkmanuals.com...
Page 331: 8-Bit Bus Timings
8XC196MC, MD, MH USER’S MANUAL 15.3.3 8-bit Bus Timings When the microcontroller is configured to operate in the 8-bit bus mode, lines AD7:0 form a mul- tiplexed lower address and data bus. Lines AD15:8 are not multiplexed; the upper address is latched and remains valid throughout the bus cycle.
Page 332: Wait States (Ready Control)
Low data out High data out (write) +1 Out † The CLKOUT pin is available only on the 8XC196MC, MD. A3164-01 Figure 15-7. Timings for 8-bit Buses 15.4 WAIT STATES (READY CONTROL) An external device can use the READY input to lengthen an external bus cycle. When an external address is placed on the bus, the external device can pull the READY signal low to indicate it is not ready.
Page 333 8XC196MC, MD, MH USER’S MANUAL After the CCB1 fetch, the internal ready control circuitry allows slow external memory devices to increase the length of the read and write bus cycles. If the external memory device is not ready for access, it pulls the READY signal low and holds it low until it is ready to complete the oper- ation, at which time it releases READY.
Page 334 Address Out Data AD15:0 (read) AD15:0 Address Address Out Data Out (write) † The CLKOUT pin is available only on the 8XC196MC, MD. A3165-01 Figure 15-8. READY Timing Diagram — One Wait State (8XC196MC, MD) 15-19 Get other manuals https://www.bkmanuals.com...
Page 335 Minimum time the level of the READY signal must be valid after CLKOUT falls. ALE Cycle Time LHLH Minimum time between ALE pulses. † This specification applies to the 8XC196MC, MD microcontrollers only. †† This specification applies to the 8XC196MH microcontroller only. 15-20 Get other manuals https://www.bkmanuals.com...
Page 336: Bus-Control Modes
XTAL All AC timings are referenced to T XTAL † This specification applies to the 8XC196MC, MD microcontrollers only. †† This specification applies to the 8XC196MH microcontroller only. 15.5 BUS-CONTROL MODES The ALE and WR bits (CCR0.3 and CCR0.2) define which bus-control signals will be generated during external read and write cycles.
Page 337: Standard Bus-Control Mode
8XC196MC, MD, MH USER’S MANUAL 15.5.1 Standard Bus-control Mode In the standard bus-control mode, the microcontroller generates the standard bus-control signals: ALE, RD#, WR#, and BHE# (see Figure 15-10). ALE is asserted while the address is driven, and it can be used to latch the address externally. RD# is asserted for every external memory read, and WR# is asserted for every external memory write.
Page 338 INTERFACING WITH EXTERNAL MEMORY Figure 15-12 shows an 8-bit system with both flash and RAM. The flash is the lower half of mem- ory, and the RAM is the upper half. This system configuration uses the most-significant address bit (AD15) as the chip-select signal and ALE as the address-latch signal. AD15 AD14:8 A14:8...
Page 339 8XC196MC, MD, MH USER’S MANUAL Figure 15-13 shows a system that uses the dynamic bus-width feature. (The CCR bits, BW0 and BW1, are set.) Code is executed from the two EPROMs and data is stored in the byte-wide RAM. The RAM is in high memory. It is selected by driving AD15 high, which also selects the 8-bit bus-width mode by driving the BUSWIDTH signal low.
Page 340: Write Strobe Mode
INTERFACING WITH EXTERNAL MEMORY 15.5.2 Write Strobe Mode The write strobe mode eliminates the need to externally decode high- and low-byte writes to an external 16-bit RAM or flash device in 16-bit bus mode. When the write strobe mode is selected, the microcontroller generates WRL# and WRH# instead of WR# and BHE#.
Page 341 8XC196MC, MD, MH USER’S MANUAL Figure 15-15 shows a 16-bit system with two EPROMs and two RAMs. It is configured to use the write strobe mode. ALE latches the address; AD15 is the chip-select signal for the memory devices. WRL# is asserted during low byte writes and word writes. WRH# is asserted during high byte writes and word writes.
Page 342: Address Valid Strobe Mode
INTERFACING WITH EXTERNAL MEMORY 15.5.3 Address Valid Strobe Mode When the address valid strobe mode is selected, the microcontroller generates the address valid signal (ADV#) instead of the address latch enable signal (ALE). ADV# is asserted after an exter- nal address is valid (see Figure 15-16). This signal can be used to latch the valid address and si- multaneously enable an external memory device.
Page 343 8XC196MC, MD, MH USER’S MANUAL Figure 15-18 and Figure 15-19 show sample circuits that use the address valid strobe mode. Fig- ure 15-18 shows a simple 8-bit system with a single flash. It is configured for the address valid strobe mode. This system configuration uses the ADV# signal as both the flash chip-select signal and the address-latch signal.
Page 344 INTERFACING WITH EXTERNAL MEMORY Figure 15-19 shows a 16-bit system with two EPROMs. This system configuration uses the ADV# signal as both the EPROM chip-select signal and the address-latch signal. BUSWIDTH A14:8 A15:8 74AC AD15:8 A13:7 A13:7 D15:8 ADV# D7:0 16K×8 16K×8 EPROM...
Page 345: Address Valid With Write Strobe Mode
8XC196MC, MD, MH USER’S MANUAL 15.5.4 Address Valid with Write Strobe Mode When the address valid with write strobe mode is selected, the microcontroller generates the ADV#, RD#, WRL#, and WRH# bus-control signals. This mode is used for a simple system us- ing an external 16-bit data bus.
Page 346: System Bus Ac Timing Specifications
INTERFACING WITH EXTERNAL MEMORY V CC BUSWIDTH A13:8 74AC AD15:8 A12:7 A12:7 D15:8 ADV# D7:0 8K×8 8K×8 8XC196 (High) (Low) A7:1 74AC AD7:0 A6:0 A6:0 WRH# WRL# A3097-01 Figure 15-21. 16-bit System with RAM 15.6 SYSTEM BUS AC TIMING SPECIFICATIONS Refer to the latest datasheet for the AC timings to make sure your system meets specifications.
Page 347 Address Out Data Out Address Out (write) WHBX RHBX Valid BHE#, INST WHAX RHAX AD15:8 Address Out (8-bit mode) † The CLKOUT pin is available only on the 8XC196MC, MD. A3166-01 Figure 15-22. System Bus Timing 15-32 Get other manuals https://www.bkmanuals.com...
Page 348: Explanation Of Ac Symbols
Floating ALE/ADV# † The CLKOUT pin is available only on the 8XC196MC, MD microcontrollers. 15.6.2 AC Timing Definitions Tables 15-8 and 15-9 define the AC timing specifications that the memory system must meet and those that the microcontroller will provide.
Page 349 Time after the microcontroller deasserts RD# until it stops driving the address on the bus. RD# Low to RD# High RLRH RD# pulse width. † The CLKOUT pin is available only on the 8XC196MC, MD microcontrollers. 15-34 Get other manuals https://www.bkmanuals.com...
Page 350 XTAL1 High to CLKOUT High or Low XHCH XTAL XTAL The period of the frequency on the XTAL1 input (F ). All AC timings are referenced to XTAL XTAL † The CLKOUT pin is available only on the 8XC196MC, MD microcontrollers. 15-35 Get other manuals https://www.bkmanuals.com...
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Page 352: Programming The Nonvolatile Memory
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Page 354: Programming Methods
CHAPTER 16 PROGRAMMING THE NONVOLATILE MEMORY The 87C196MC and 87C196MD contain 16 Kbytes of one-time-programmable read-only mem- ory (OTPROM); the 87C196MH contains 32 Kbytes. OTPROM is similar to EPROM, but it comes in an unwindowed package and cannot be erased. You can either program the OTPROM yourself or have the factory program it as a quick-turn ROM product (this option may not be available for all devices).
Page 355: Otprom Memory Map
8XC196MH, PCCB and UPROM modes allow you to program those locations. For the 8XC196MC and 8XC196MD, only slave mode allows you to program them.) After programming, you can use the ROM-dump mode to write the entire OTPROM array to an external memory device to verify its contents.
Page 356: Security Features
PCCB programming modes allow you to program the PCCBs. NOTE The developers have made a substantial effort to provide an adequate program protection scheme. However, Intel cannot and does not guarantee that these protection methods will always prevent unauthorized access. 16-3...
Page 357: Controlling Access To The Otprom During Normal Operation
8XC196MC, MD, MH USER’S MANUAL 16.3.1.1 Controlling Access to the OTPROM During Normal Operation During normal operation, the lock bits in CCB0 control read and write accesses to the OTPROM. Table 16-2 describes the options. You can program the CCBs using any of the programming methods.
Page 358 PROGRAMMING THE NONVOLATILE MEMORY These protection levels are provided by the PCCB0 lock bits, the CCB0 lock bits, and the internal security key (Table 16-3). When entering programming modes, the reset sequence loads the PCCBs into the chip configuration registers. It also loads CCB0 into internal RAM to provide an additional level of security.
Page 359: Controlling Fetches From External Memory
8XC196MC, MD, MH USER’S MANUAL You can program the internal security key in either auto or slave programming mode. Once the security key is programmed, you must provide a matching key to gain access to any programming mode. For auto programming and ROM-dump modes, a matching security key must reside in ex- ternal memory.
Page 360 You can verify a UPROM bit to make sure it programmed, but you cannot erase it. For this reason, Intel cannot test the bits before shipment. However, Intel does test the features that the UPROM bits enable, so the only undetectable defects are (unlikely) defects within the UPROM cells them- selves.
Page 361: Programming Pulse Width
The programming pulse width (PPW) register is loaded from the external EPROM (locations 14H and 15H for the 8XC196MC and MD; locations 4014H and 4015H for the 8XC196MH) in auto programming mode. The PPW_VALUE determines the programming pulse width.
Page 362: Modified Quick-Pulse Algorithm
A verification error deasserts the PVER signal, but does not stop the programming routine. This process repeats until each OTPROM word has been programmed and verified. Intel guarantees lifetime data retention for a device pro- grammed with the modified quick-pulse algorithm.
Page 363 8XC196MC, MD, MH USER’S MANUAL From Auto or Slave Programming Start PPW Timer Write Data to OTPROM Enable Interrupts Enter Idle Mode Wait for PPW Timer Interrupt Required Writes Done Compare Programmed Locations and Set Flags Return A0190-03 Figure 16-3. Modified Quick-pulse Algorithm Auto programming repeats the pulse twice (for the 87C196MC, MD) or five times (for the 87C196MH), using the pulse width you specify in the external EPROM.
Page 364: Programming Mode Pins
PROGRAMMING THE NONVOLATILE MEMORY 16.6 PROGRAMMING MODE PINS Figure 16-4 illustrates the signals used in programming and Table 16-6 describes them. The EA#, , and PMODE pins combine to control entry into programming modes. You must configure the PMODE (P0.7:4) pins to select the desired programming mode (see Table 16-7 on page 16-13).
Page 365 8XC196MC, MD, MH USER’S MANUAL Table 16-6. Pin Descriptions (Continued) Special- Program- Port Pin function Type ming Description Signal Mode P2.2 PROG# Slave Programming During programming, a falling edge latches data on the PBUS and begins programming, while a rising edge ends programming.
Page 366: Entering Programming Modes
PROGRAMMING THE NONVOLATILE MEMORY Table 16-6. Pin Descriptions (Continued) Special- Program- Port Pin function Type ming Description Signal Mode — External Access Controls program mode entry. If EA# is at V voltage on the rising edge of RESET#, the device enters programming mode.
Page 367: Power-Up And Power-Down Sequences
8XC196MC, MD, MH USER’S MANUAL 16.7.2 Power-up and Power-down Sequences When you are ready to begin programming, follow these power-up and power-down procedures. WARNING Failure to observe these warnings will cause permanent device damage. • Voltage must not be applied to V while V is low.
Page 368: Slave Programming Mode
PROGRAMMING THE NONVOLATILE MEMORY 16.8 SLAVE PROGRAMMING MODE Slave programming mode allows you to program and verify the entire OTPROM array, including the PCCBs and UPROM bits, by using an EPROM programmer. In this mode, ports 3 and 4 serve as the PBUS, transferring commands, addresses, and data. The least-significant bit of the PBUS (P3.0) controls the command (1 = program word;...
Page 369: Slave Programming Circuit And Memory Map
8XC196MC, MD, MH USER’S MANUAL Table 16-8. Device Signature Word and Programming Voltages Signature Word Programming V Programming V Device Location Value Location Value Location Value 8XC196MC, MD 0070H 8794H 0072H 0073H 0A0H 8XC196MH 0070H 87DEH 0072H 0073H 0A0H 16.8.2 Slave Programming Circuit and Memory Map Figure 16-5 shows the circuit diagram and Table 16-9 shows the memory map for slave program- ming mode.
Page 370: Operating Environment
PROGRAMMING THE NONVOLATILE MEMORY Table 16-9. Slave Programming Mode Memory Map Description Address Comments OTPROM (MH) 2000–9FFFH OTPROM Cells (MC, MD) 2000–5FFFH † 0758H UPROM Cell † 0718H UPROM Cell PCCB 0218H Test EPROM Programming voltages (see Table 16-8 on page 16-16) 0072H, 0073H Read Only Signature word 0070H Read Only...
Page 371 8XC196MC, MD, MH USER’S MANUAL no direct access CCR1, CCR0 The chip configuration registers (CCRs) control wait states, powerdown mode, and internal memory protection. These registers are loaded from the PCCBs during programming modes and from the CCBs for normal operation.
Page 372: Slave Programming Routines
PROGRAMMING THE NONVOLATILE MEMORY 16.8.4 Slave Programming Routines The slave programming mode algorithm consists of three routines: the address/command decod- ing routine, the program word routine, and the dump word routine. The address/command decoding routine (Figure 16-7) reads the PBUS and transfers control to the program word or dump word routine based on the value of P3.0.
Page 373 8XC196MC, MD, MH USER’S MANUAL Other PMODE = 05H Modes PALE# (P2.1) = 0 Read Data From PBUS PVER Deassert CPVER (P2.0) = 1 Assert PVER PALE# (P2.1)= 0 Check Address Dump Word P3.0 = 1 Routine Program Word Routine A0193-02 Figure 16-7.
Page 374 PROGRAMMING THE NONVOLATILE MEMORY From Address/ Command Decoder PROG# (P2.2)=0 Lock Bits Verify Read Data Security Key Enabled from PBUS Execute Modified Keys Loop Quick-Pulse Algorithm Match Forever then Return Deassert Programming PVER (P2.0 = 0) Verifies Read Data from PBUS Assert PVER (P2.0 = 1) PROG#...
Page 375 8XC196MC, MD, MH USER’S MANUAL Figure 16-9 shows the timings of the program word command with a repeated programming pulse and auto increment. Asserting PALE# latches the command and address on the PBUS. Asserting PROG# latches the data on the PBUS and starts the programming sequence. The PROG# signal controls the programming pulse width.
Page 376 PROGRAMMING THE NONVOLATILE MEMORY From Address/ Command Decoder Lock Bits Enabled Get Data from OPTROM PROG# (P2.2) = 0 Write Data to PBUS PROG# (P2.2) = 1 Write 0FFFFH to PBUS PALE# To Address/ (P2.1) = 0 Command Decoder AINC# (P2.4) = 0 Increment Address by 2...
Page 377: Timing Mnemonics
8XC196MC, MD, MH USER’S MANUAL Figure 16-11 shows the timings of the dump word command. PROG# governs when the device drives the bus. The timings before the dump word command are the same as those shown in Fig- ure 16-9. In the dump word mode, the AINC# pin can remain active and toggling. The PROG# pin automatically increments the address.
Page 378: Auto Programming Mode
Figure 16-12 shows the recommended circuit for auto programming mode. Table 16-11 shows the 8XC196MC/MD memory map and Table 16-11 shows the 8XC196MH auto programming mem- ory map. Auto programming is specified for a crystal frequency of 6 to 8 MHz. At 8 MHz, use a 27(C)512 EPROM with tACC = 250 ns and tOE = 100 ns or faster specifications.
Page 379 8XC196MC, MD, MH USER’S MANUAL 20 pF 20 pF 100 kΩ XTAL1 XTAL2 Reset RESET# +5.0V 1 kΩ 74HC14 1.0µF READY/P5.6 10µF BUSWIDTH/P5.7 +12.50V P0.7/ RD#/P5.3 PMODE.3 P0.6/ PMODE.2 P1.3:0 P0.5/ AD11:8 PMODE.1 A15:8 MC/MD P0.4/ AD15:8 PMODE.0 ANGND LE OE# 270kΩ...
Page 380: Operating Environment
PROGRAMMING THE NONVOLATILE MEMORY Table 16-11. 8XC196MC/MD Auto Programming Memory Map Address Address Using Internal Output from Circuit in OTPROM Description 8XC196MC, Figure 16-12 Address 8XC196MD (A15:0) 4014H 14H Programming pulse width (PPW) LSB. 4015H 15H Programming pulse width (PPW) MSB.
Page 381 8XC196MC, MD, MH USER’S MANUAL Other PMODE = 0CH Modes Lock Bits Enabled Verify Security Key Loop Pass Forever Assert PACT# Load PPW Get External Data Data = 0FFFFH Execute Modified Quick-Pulse Algorithm then Return Error Programming Clear PVER Increment Address Pointer...
Page 382: Auto Programming Procedure
OTPROM array, including the security key. — Place the programming pulse width (PPW) in external EPROM locations 14H–15H (for the 8XC196MC, MD) or 105E–105FH (for the 8XC196MH). — Leave the external CCB0 location (4018H) unprogrammed (0FFFFH).
Page 383: Rom-Dump Mode
8XC196MC, MD, MH USER’S MANUAL Using another blank EPROM device, follow these steps to program only CCB0. — Place the programming pulse width (PPW) in external locations 14H–15H. — Place the appropriate CCB0 value in external location 4018H. — Place the security key to be verified in external EPROM locations 0020H–002FH. This value must match the security key programmed in step 1.
Page 384 PROGRAMMING THE NONVOLATILE MEMORY Figure 16-14 shows the recommended circuit for PCCB and UPROM programming. In these cir- cuits, the PBUS holds data to be written to the OTPROM, PALE# begins programming, and PVER drives an LED that lights to indicate successful programming. 20 pF 20 pF 100 kΩ...
Page 385: Run-Time Programming
8XC196MC, MD, MH USER’S MANUAL Table 16-13. PCCB and UPROM Programming Values Pins PCCB Programming UPROM Programming PMODE3:0 P4.7:0 P3.7:0 Data to be programmed in PCCB Value to program UPROM bits: (See CCR descriptions in Appendix C) 04H to program DED only...
Page 386 PROGRAMMING THE NONVOLATILE MEMORY The calling routine must pass two parameters to this routine — the data to be programmed (in DATA_TEMP) and the address (in ADDR_TEMP). PROGRAM: PUSHA ;clear PSW, WSR, INT_MASK, INT_MASK1 WSR,#7BH ;select 32-byte window with EPA0_CON COUNT,#5 ;set up for 5 programming cycles ANDB INT_PEND,#CLEAR_EPA0...
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Page 390 APPENDIX A INSTRUCTION SET REFERENCE ® This appendix provides reference information for the instruction set of the family of MCS microcontrollers. It defines the processor status word (PSW) flags, describes each instruction, shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes, instruction lengths, and execution times.
Page 391 8XC196MC, MD, MH USER’S MANUAL Table A-1. Opcode Map (Left Half) Opcode SKIP CLRB NOTB NEGB XCHB DECB EXTB INCB SJMP bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 AND 3op ADD 3op...
Page 392 INSTRUCTION SET REFERENCE Table A-1. Opcode Map (Right Half) Opcode SHRA SHRL SHLL SHRAL NORML SHRB SHLB SHRAB XCHB SCALL bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 SUB 3op MULU 3op (Note 2) SUBB 3op MULUB 3op (Note 2) SUB 2op...
Page 393 8XC196MC, MD, MH USER’S MANUAL Table A-2. Processor Status Word (PSW) Flags Mnemonic Description The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of the last bit shifted out of an operand. If a subtraction operation generates a borrow, the carry flag is cleared.
Page 394 INSTRUCTION SET REFERENCE Table A-3 shows the effect of the PSW flags or a specified condition on conditional jump instruc- tions. Table A-4 defines the symbols used in Table A-6 to show the effect of each instruction on the PSW flags. Table A-3.
Page 395 8XC196MC, MD, MH USER’S MANUAL Table A-5 defines the variables that are used in Table A-6 to represent the instruction operands. Table A-5. Operand Variables Variable Description A 2-bit field within an opcode that selects the basic addressing mode used. This field is present only in those opcodes that allow addressing mode options.
Page 396 INSTRUCTION SET REFERENCE Table A-6. Instruction Set Mnemonic Operation Instruction Format ADD WORDS. Adds the source and DEST, SRC (2 operands) destination word operands and stores the wreg, waop sum into the destination operand. (011001aa) (waop) (wreg) ← (DEST) (DEST) + (SRC) PSW Flag Settings ↑...
Page 397 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ADDCB ADD BYTES WITH CARRY. Adds the source DEST, SRC and destination byte operands and the carry ADDCB breg, baop flag (0 or 1) and stores the sum into the (101101aa) (baop) (breg) destination operand.
Page 398 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format ANDB LOGICAL AND BYTES. ANDs the two source DEST, SRC1, SRC2 (3 operands) byte operands and stores the result into the ANDB Dbreg, Sbreg, baop destination operand. The result has ones in (010100aa) (baop) (Sbreg) (Dbreg) only the bit positions in which both operands had a “1”...
Page 399 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format BMOVI INTERRUPTIBLE BLOCK MOVE. Moves a PTRS, CNTREG block of word data from one location in BMOVI lreg, wreg memory to another. The instruction is (11001101) (wreg) (lreg) identical to BMOV, except that BMOVI is interruptible.
Page 400 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format CLRB CLEAR BYTE. Clears the value of the DEST operand. CLRB breg ← (DEST) (00010001) (breg) PSW Flag Settings — — CLRC CLEAR CARRY FLAG. Clears the carry flag. ←...
Page 401 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format CMPL COMPARE LONG. Compares the DEST, SRC magnitudes of two double-word (long) CMPL Dlreg, Slreg operands. The operands are specified using (11000101) (Slreg) (Dlreg) the direct addressing mode. The flags are altered, but the operands remain unaffected.
Page 402 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DIVIDE INTEGERS. Divides the contents of DEST, SRC the destination long-integer operand by the lreg, waop contents of the source integer word operand, (11111110) (100011aa) (waop) (lreg) using signed arithmetic. It stores the quotient into the low-order word of the destination (i.e., the word with the lower address) and the remainder into the high-order word.
Page 403 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DIVUB DIVIDE BYTES, UNSIGNED. This instruction DEST, SRC divides the contents of the destination word DIVUB wreg, baop operand by the contents of the source byte (100111aa) (baop) (wreg) operand, using unsigned arithmetic.
Page 404 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format DPTS DISABLE PERIPHERAL TRANSACTION SERVER (PTS). Disables the peripheral DPTS transaction server (PTS). (11101100) ← PTS Disable (PSW.2) PSW Flag Settings — — — — — — ENABLE INTERRUPTS. Enables interrupts following the execution of the next statement.
Page 405 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format EXTB SIGN-EXTEND SHORT-INTEGER INTO INTEGER. Sign-extends the low-order byte EXTB wreg of the operand throughout the high-order byte (00010110) (wreg) of the operand. if DEST.7 = 1 then ←...
Page 406 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format INCB INCREMENT BYTE. Increments the value of the byte operand by 1. INCB breg ← (DEST) (DEST) + 1 (00010111) (breg) PSW Flag Settings ↑ — JUMP IF BIT IS CLEAR. Tests the specified bit.
Page 407 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF CARRY FLAG IS SET. Tests the carry flag. If the carry flag is clear, control cadd passes to the next sequential instruction. If (11011011) (disp)
Page 408 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF SIGNED GREATER THAN. Tests both the zero flag and the negative flag. If cadd either flag is set, control passes to the next (11010010) (disp) sequential instruction. If both flags are clear, this instruction adds to the program counter the offset between the end of this instruction NOTE: The displacement (disp) is sign-...
Page 409 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF SIGNED LESS THAN. Tests the negative flag. If the flag is clear, control cadd passes to the next sequential instruction. If (11011110) (disp) the negative flag is set, this instruction adds...
Page 410 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF NOT HIGHER (UNSIGNED). Tests both the zero flag and the carry flag. If the cadd carry flag is set and the zero flag is clear, (11010001) (disp) control passes to the next sequential instruction.
Page 411 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JNVT JUMP IF OVERFLOW-TRAP FLAG IS CLEAR. Tests the overflow-trap flag. If the JNVT cadd flag is set, this instruction clears the flag and (11010100) (disp) passes control to the next sequential instruction.
Page 412 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format JUMP IF OVERFLOW-TRAP FLAG IS SET. Tests the overflow-trap flag. If the flag is clear, cadd control passes to the next sequential (11011100) (disp) instruction. If the overflow-trap flag is set, this instruction clears the flag and adds to the program counter the offset between the end NOTE: The displacement (disp) is sign-...
Page 413 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format LDBSE LOAD BYTE SIGN-EXTENDED. Sign- DEST, SRC extends the value of the source short- LDBSE wreg, baop integer operand and loads it into the (101111aa) (baop) (wreg) destination integer operand.
Page 414 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULTIPLY INTEGERS. Multiplies the source DEST, SRC (2 operands) and destination integer operands, using lreg, waop signed arithmetic, and stores the 32-bit result (11111110) (011011aa) (waop) (lreg) into the destination long-integer operand. The sticky bit flag is undefined after the instruction is executed.
Page 415 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format MULU MULTIPLY WORDS, UNSIGNED. Multiplies DEST, SRC (2 operands) the source and destination word operands, MULU lreg, waop using unsigned arithmetic, and stores the 32- (011011aa) (waop) (lreg) bit result into the destination double-word operand.
Page 416 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format NEGATE INTEGER. Negates the value of the integer operand. wreg ← (DEST) – (DEST) (00000011) (wreg) PSW Flag Settings ↑ — NEGB NEGATE SHORT-INTEGER. Negates the value of the short-integer operand. NEGB breg ←...
Page 417 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format COMPLEMENT WORD. Complements the value of the word operand (replaces each “1” wreg with a “0” and each “0” with a “1”). (00000010) (wreg) ← (DEST)
Page 418 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format POP WORD. Pops the word on top of the stack and places it at the destination waop operand. (110011aa) (waop) ← (DEST) (SP) ← SP + 2 PSW Flag Settings —...
Page 419 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format PUSHA PUSH ALL. This instruction is used instead of PUSHF, to support the eight additional PUSHA interrupts. It pushes two words — (11110100) PSW/INT_MASK and INT_MASK1/WSR —...
Page 420 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format RESET SYSTEM. Initializes the PSW to zero, the PC to 2080H, and the pins and SFRs to their reset values. Executing this instruction (11111111) causes the RESET# pin to be pulled low for 16 state times.
Page 421 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHIFT WORD LEFT. Shifts the destination word operand to the left as many times as wreg, #count specified by the count operand. The count (00001001) (count) (wreg)
Page 422 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHLL SHIFT DOUBLE-WORD LEFT. Shifts the destination double-word operand to the left SHLL lreg, #count as many times as specified by the count (00001101) (count) (lreg) operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, or as the content of any SHLL...
Page 423 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRA ARITHMETIC RIGHT SHIFT WORD. Shifts the destination word operand to the right as SHRA wreg, #count many times as specified by the count (00001010) (count) (wreg) operand.
Page 424 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRAL ARITHMETIC RIGHT SHIFT DOUBLE- WORD. Shifts the destination double-word SHRAL lreg, #count operand to the right as many times as (00001110) (count) (lreg) specified by the count operand. The count may be specified either as an immediate value in the range of 0 to 15 (0FH), inclusive, SHRAL...
Page 425 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SHRL LOGICAL RIGHT SHIFT DOUBLE-WORD. Shifts the destination double-word operand to SHRL lreg, #count the right as many times as specified by the (00001100) (count) (lreg) count operand.
Page 426 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format STORE WORD. Stores the value of the SRC, DEST source (leftmost) word operand into the wreg, waop destination (rightmost) operand. (110000aa) (waop) (wreg) ← (DEST) (SRC) PSW Flag Settings —...
Page 427 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format SUBB SUBTRACT BYTES. Subtracts the source DEST, SRC (2 operands) byte operand from the destination byte SUBB breg, baop operand, stores the result in the destination...
Page 428 INSTRUCTION SET REFERENCE Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format TIJMP TABLE INDIRECT JUMP. Causes execution to continue at an address selected from a TIJMP TBASE, [INDEX], #MASK table of addresses. (11100010) [INDEX] (#MASK) (TBASE) The first word register, TBASE, contains the 16-bit address of the beginning of the jump table.
Page 429 8XC196MC, MD, MH USER’S MANUAL Table A-6. Instruction Set (Continued) Mnemonic Operation Instruction Format EXCHANGE WORD. Exchanges the value of DEST, SRC the source word operand with that of the wreg, waop destination word operand. (00000100) (waop) (wreg) direct ↔...
Page 430 INSTRUCTION SET REFERENCE Table A-7 lists the instruction opcodes, in hexadecimal order, along with the corresponding in- struction mnemonics. Table A-7. Instruction Opcodes Hex Code Instruction Mnemonic SKIP XCH Direct SHRA XCH Indexed SHRL SHLL SHRAL NORML Reserved CLRB NOTB NEGB XCHB Direct DECB...
Page 431 8XC196MC, MD, MH USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic ADD Immediate (3 ops) ADD Indirect (3 ops) ADD Indexed (3 ops) SUB Direct (3 ops) SUB Immediate (3 ops) SUB Indirect (3 ops) SUB Indexed (3 ops)
Page 432 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic MULU Indirect (2 ops) MULU Indexed (2 ops) ANDB Direct (2 ops) ANDB Immediate (2 ops) ANDB Indirect (2 ops) ANDB Indexed (2 ops) ADDB Direct (2 ops) ADDB Immediate (2 ops) ADDB Indirect (2 ops) ADDB Indexed (2 ops)
Page 433 8XC196MC, MD, MH USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic XORB Indexed CMPB Direct CMPB Immediate CMPB Indirect CMPB Indexed DIVUB Direct DIVUB Immediate DIVUB Indirect DIVUB Indexed LD Direct LD Immediate LD Indirect LD Indexed...
Page 434 INSTRUCTION SET REFERENCE Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic ST Direct BMOV ST Indirect ST Indexed STB Direct CMPL STB Indirect STB Indexed PUSH Direct PUSH Immediate PUSH Indirect PUSH Indexed POP Direct BMOVI POP Indirect POP Indexed JNST JNVT DJNZ...
Page 435 8XC196MC, MD, MH USER’S MANUAL Table A-7. Instruction Opcodes (Continued) Hex Code Instruction Mnemonic PUSHF POPF PUSHA POPA IDLPD TRAP CLRC SETC CLRVT DIV/DIVB/MUL/MULB (Note 2) NOTES: This opcode is reserved, but it does not generate an unimplemented opcode interrupt.
Page 436 INSTRUCTION SET REFERENCE Table A-8 lists instructions along with their lengths and opcodes for each applicable addressing mode. A dash (—) in any column indicates “not applicable.” Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic (Group I) Indexed Direct Immediate Indirect (Note 1) Mnemonic...
Page 437 8XC196MC, MD, MH USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Arithmetic (Group II) Indexed Direct Immediate Indirect (Note 1) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode FE 8C FE 8D FE 8E FE 8F DIVB...
Page 438 INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Stack Indexed Direct Immediate Indirect (Note 1) Mnemonic Length Length Opcode Length Opcode Length Opcode Opcode — — POPA — — — — — — POPF — — — —...
Page 439 8XC196MC, MD, MH USER’S MANUAL Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Call Indexed Direct Immediate Indirect (Note 1) Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode LCALL — — — — — — — — — —...
Page 440 INSTRUCTION SET REFERENCE Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued) Shift Direct Immediate Indirect Indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode NORML — — — — — — — — — — — — SHLB — —...
Page 441 8XC196MC, MD, MH USER’S MANUAL Table A-9 lists instructions alphabetically within groups, along with their execution times, ex- pressed in state times. Table A-9. Instruction Execution Times (in State Times) Arithmetic (Group I) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc.
Page 442 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Arithmetic (Group II) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem. DIVB DIVU DIVUB MUL (2 ops) MUL (3 ops) MULB (2 ops) MULB (3 ops) MULU (2 ops)
Page 443 8XC196MC, MD, MH USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Stack (Register) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem. — POPA — — — — —...
Page 444 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Data Mnemonic Indirect BMOV register/register 6 + 8 per word memory/register 6 + 11 per word memory/memory 6 + 14 per word BMOVI register/register 7 + 8 per word + 14 per interrupt memory/register 7 + 11 per word + 14 per interrupt memory/memory...
Page 445 8XC196MC, MD, MH USER’S MANUAL Table A-9. Instruction Execution Times (in State Times) (Continued) Call (Memory) Indirect Indexed Mnemonic Direct Immed. Normal Autoinc. Short Long LCALL — — — — — — — — — — SCALL — — —...
Page 446 INSTRUCTION SET REFERENCE Table A-9. Instruction Execution Times (in State Times) (Continued) Shift Mnemonic Direct NORML 8 + 1 per shift (9 for 0 shift) 6 + 1 per shift (7 for 0 shift) SHLB 6 + 1 per shift (7 for 0 shift) SHLL 7 + 1 per shift (8 for 0 shift) 6 + 1 per shift (7 for 0 shift)
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Page 448 Signal Descriptions Get other manuals https://www.bkmanuals.com...
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Page 450 COMP x FUNCTIONAL GROUPINGS OF SIGNALS Tables B-2, B-3, and B-4 list the signals for the 8XC196MC, 8XC196MD, and 8XC196MH re- spectively, grouped by function. A diagram of each package that is currently available shows the pin location of each signal.
Page 451 8XC196MC, MD, MH USER’S MANUAL Table B-2. 8XC196MC Signals Arranged by Functional Categories Address & Data Programming Control Input/Output Input/Output (Cont’d) AD15:0 AINC# P0.7:0/ACH7:0 P6.5/WG3 CPVER P1.0/ACH8 P6.6/PWM0 Bus Control & Status PACT# P1.1/ACH9 P6.7/PWM1 ALE/ADV# PALE# P1.2/ACH10/T1CLK BHE#/WRH# PBUS.15:0 P1.3/ACH11/T1DIR...
Page 452 P1.2 / ACH10 / T1CLK P1.3 / ACH11 / T1DIR P6.5 / WG3 P6.0 / WG1# P6.4 / WG3# P6.1 / WG1 P6.3 / WG2 P6.2 / WG2# A3103-02 Figure B-1. 8XC196MC 64-lead Shrink DIP (SDIP) Package Get other manuals https://www.bkmanuals.com...
Page 453 P0.4 / ACH4 / PMODE.0 AD2 / P3.2 / PBUS.2 P0.5 / ACH5 / PMODE.1 AD1 / P3.1 / PBUS.1 AD0 / P3.0 / PBUS.0 ANGND P0.6 / ACH6 / PMODE.2 A3101-02 Figure B-2. 8XC196MC 84-lead PLCC Package Get other manuals https://www.bkmanuals.com...
Page 454 AD1 / P3.1 / PBUS.1 P0.4 / ACH4 / PMODE.0 AD0 / P3.0 / PBUS.0 P0.5 / ACH5 / PMODE.1 RESET# ANGND P0.6 / ACH6 / PMODE.2 P0.7 / ACH7 / PMODE.3 A3104-01 Figure B-3. 8XC196MC 80-lead Shrink EIAJ/QFP Package Get other manuals https://www.bkmanuals.com...
Page 455 8XC196MC, MD, MH USER’S MANUAL Table B-3. 8XC196MD Signals Arranged by Functional Categories Address & Data Programming Control Input/Output Input/Output (Cont’d) AD15:0 AINC# P0.7:0/ACH7:0 P7.1:0/EPA5:4 CPVER P1.1:0/ACH9:8 P7.3:2/COMP5:4 Bus Control & Status PACT# P1.2/ACH10/T1CLK P7.6:4 ALE/ADV# PALE# P1.3/ACH11/T1DIR P7.7/FREQOUT BHE#/WRH# PBUS.15:0...
Page 456 SIGNAL DESCRIPTIONS AD15 / P4.7 / PBUS.15 P2.5 / COMP1 / PACT# AD14 / P4.6 / PBUS.14 P2.4 / COMP0 / AINC# P7.3 / COMP5 AD13 / P4.5 / PBUS.13 P7.2 / COMP4 CLKOUT P2.7 / COMP3 AD12 / P4.4 / PBUS.12 P2.3 / EPA3 AD11 / P4.3 / PBUS.11 P2.2 / EPA2 / PROG#...
Page 457 8XC196MC, MD, MH USER’S MANUAL P5.2 / WR# / WRL# P6.7 / PWM1 P5.7 / BUSWIDTH P2.6 / COMP2 / CPVER AD15 / P4.7 / PBUS.15 P2.5 / COMP1 / PACT# AD14 / P4.6 / PBUS.14 P2.4 / COMP0 / AINC# P7.3 / COMP5...
Page 458 SIGNAL DESCRIPTIONS Table B-4. 8XC196MH Signals Arranged by Functional Categories Address & Data Programming Control Input/Output Input/Output (Cont’d) AD15:0 AINC# P0.5:0/ACH5:0 P5.0 CPVER P0.6/ACH6/T1CLK P5.1 Bus Control & Status PACT# P0.7/ACH7/T1DIR P5.7:2 ALE/ADV# PALE# P1.0/TXD0 P6.0/WG1# BHE#/WRH# PBUS.15:0 P1.1/RXD0 P6.1/WG1 BUSWIDTH PMODE.3:0 P1.2/TXD1...
Page 459 8XC196MC, MD, MH USER’S MANUAL P5.6 / READY P5.0 / ALE / ADV# P5.4 / ONCE# EXTINT P5.3 / RD# P5.5 / BHE# / WRH# XTAL1 P5.2 / WR# / WRL# XTAL2 P5.7 / BUSWIDTH P6.6 / PWM0 AD14 / P4.6 / PBUS.14 P2.7 / SCLK1# / BCLK1...
Page 460 SIGNAL DESCRIPTIONS AD15 / P4.7 / PBUS.15 P2.5 / COMP1 / PACT# AD14 / P4.6 / PBUS.14 P2.4 / COMP0 / AINC# AD13 / P4.5 / PBUS.13 P2.7 / SCLK1# / BCLK1 AD12 / P4.4 / PBUS.12 P2.3 / COMP3 AD11 / P4.3 / PBUS.11 P2.2 / EPA1 / PROG# AD10 / P4.2 / PBUS.10...
Page 461 8XC196MC, MD, MH USER’S MANUAL P5.2 / WR# / WRL# P6.7 / PWM1 P5.7 / BUSWIDTH P2.6 / COMP2 / CPVER P4.7 / AD15 / PBUS.15 P2.5 / COMP1 / PACT# P4.6 / AD14 / PBUS.14 P2.4 / COMP0 / AINC# P4.5 / AD13 / PBUS.13...
Page 462 ACH7:0 are multiplexed as follows: ACH0/P0.0, ACH1/P0.1, ACH2/P0.2, ACH3/P0.3, ACH4/P0.4/PMODE.0, ACH5/P0.5/PMODE.1, ACH6/P0.6/PMODE.2, ACH7/P0.7/PMODE.3, ACH8/P1.0, ACH9/P1.1, ACH10/P1.2/T1CLK, ACH11/P1.3/T1DIR, and ACH12/P1.4, and ACH13/P1.5. ACH13 is not implemented on the 8XC196MC and ACH13:8 are not implemented on the 8XC196MH. AD15:0 Address/Data Lines These pins provide a multiplexed address and data bus. During the address phase of the bus cycle, address bits 0–15 are presented on the bus and can be...
Page 463 ALE is multiplexed with P5.0 and ADV#. ANGND Analog Ground ANGND must be connected for A/D converter and port 0 operation (also Port 1 on the 8XC196MC and MD). ANGND and V should be nominally at the same potential. BCLK1:0...
Page 464 COMP5:0 are multiplexed as follows: COMP0/P2.4/AINC#, COMP1/P2.5/PACT#, COMP2/P2.6/CPVER, COMP3/P2.7(MC, MD), COMP3/P2.3 (MH), COMP4/P7.2, and COMP5/P7.3. COMP4 and COMP5 are not implemented on the 8XC196MC and MH. CPVER Cumulative Program Verification During slave programming, a high signal indicates that all locations programmed correctly, while a low signal indicates that an error occurred during one of the programming operations.
Page 465 EPA1:0 (MH) EPA5:0 are multiplexed as follows: EPA0/P2.0/PVER, EPA1/P2.1/PALE# (MC, MD), EPA1/P2.2/PROG# (MH), EPA2/P2.2/PROG#, EPA3/P2.3, EPA4/P7.0, and EPA5/P7.1. EPA5:4 are not implemented on the 8XC196MC and EPA5:2 are not implemented on the 8XC196MH. EXTINT External Interrupt This programmable interrupt is controlled by the WG_PROTECT register. This register controls whether the interrupt is edge triggered or sampled and whether a rising edge/high level or falling edge/low level activates the interrupt.
Page 466 P1.7:0 (MD) This is a high-impedance, input-only port. On the 8XC196MC and MD, some port 1 pins may individually be used as analog inputs (ACH x ) or digital inputs (P1. y ). While it is possible for the pins to...
Page 467 V specification (see datasheet) to prevent inadvertent entry into ONCE mode. On the 8XC196MC and MD, port 2 is multiplexed as follows: P2.0/EPA0/PVER, P2.1/EPA1/PALE#, P2.2/EPA2/PROG#, P2.3/EPA3, P2.4/COMP0/AINC#, P2.5/COMP1/PACT#, P2.6/COMP2/CPVER, and P2.7/COMP3.
Page 468 PBUS.7:0 are multiplexed with AD7:0 and P3.7:0. PBUS.15:8 are multiplexed with AD15:8 and P4.7:0. Auto programming: On the 8XC196MC, MC, and MH, PBUS.7:0 are multiplexed with AD7:0 and P3.7:0. On the 8XC196MC and MD, PBUS.13:8 are multiplexed with AD13:8 and P4.5:0;...
Page 469 During a word dump, a falling edge causes the contents of an OTPROM location to be output on the PBUS, while a rising edge ends the data transfer. On the 8XC196MC and MD, PROG# is multiplexed with P2.2 and EPA2. On the 8XC196MH, PROG# is multiplexed with P2.2 and EPA1.
Page 470 Reference Voltage for the A/D Converter This pin also supplies operating voltage to both the analog portion of the A/D converter and the logic used to read port 0 (also port 1 in the 8XC196MC and 8XC196MD). Digital Circuit Ground These pins supply ground for the digital circuitry.
Page 471 DEFAULT CONDITIONS Table B-8 lists the values of the signals of the 8XC196MC and 8XC196MD during various oper- ating conditions. The shaded rows indicate those signals that are available only on the B-22 Get other manuals https://www.bkmanuals.com...
Page 472 High impedance Weak pull-down LoZ0 Low impedance; strongly driven low Weak pull-up LoZ1 Low impedance; strongly driven high ODIO Open-drain I/O Table B-8. 8XC196MC and MD Default Signal Conditions Upon RESET# Alternate During Port Signals Inactive Idle Powerdown Functions RESET# Active (Note 14) P0.7:0...
Page 473 8XC196MC, MD, MH USER’S MANUAL Table B-8. 8XC196MC and MD Default Signal Conditions (Continued) Upon RESET# Alternate During Port Signals Inactive Idle Powerdown Functions RESET# Active (Note 14) P6.3 (Note 13) (Note 13) P6.4 WG3# (Note 13) (Note 13) P6.5...
Page 474 SIGNAL DESCRIPTIONS Table B-9. 8XC196MH Default Signal Conditions Upon During Alternate RESET# Port Signals RESET# Idle Powerdown Functions Inactive Active (Note 12) P0.5:0 ACH5:0 — P0.6 ACH6/T1CLK — P0.7 ACH7/T1DIR — P1.0 TXD0 (Note 10) (Note 10) P1.1 RXD0 (Note 10) (Note 10) P1.2 TXD1...
Page 475 8XC196MC, MD, MH USER’S MANUAL Table B-9. 8XC196MH Default Signal Conditions (Continued) Upon During Alternate RESET# Port Signals RESET# Idle Powerdown Functions Inactive Active (Note 12) — XTAL1 Osc input, HiZ — Osc input, HiZ Osc input, HiZ — XTAL2 Osc output, —...
Page 476 Registers Get other manuals https://www.bkmanuals.com...
Page 477 Get other manuals https://www.bkmanuals.com...
Page 478 WG_RELOAD † For the 8XC196MC, x = 2, 5; for the 8XC196MD, x = 2, 5, 7; for the 8XC196MH, x = 1, 2, 5. †† For the 8XC196MC and 8XC196MH, x = 0–5; for the 8XC196MD, x = 0–5, 7.
Page 479 8XC196MC, MD, MH USER’S MANUAL Table C-2. Register Name, Address, and Reset Status Binary Reset Value Register Register Name Mnemonic Addr High AD_COMMAND A/D Command 1FAC 1000 0000 AD_RESULT (MC, MD) 1111 1111 1100 0000 A/D Result 1FAA AD_RESULT (MH)
Page 480 REGISTERS Table C-2. Register Name, Address, and Reset Status (Continued) Binary Reset Value Register Register Name Mnemonic Addr High EPA1_TIME EPA Capture/Comp 1 Time 1F46 XXXX XXXX XXXX XXXX EPA2_TIME (MC, MD) EPA Capture/Comp 2 Time 1F4A XXXX XXXX XXXX XXXX EPA3_TIME (MC, MD) EPA Capture/Comp 3 Time...
Page 481 8XC196MC, MD, MH USER’S MANUAL Table C-2. Register Name, Address, and Reset Status (Continued) Binary Reset Value Register Register Name Mnemonic Addr High P7_PIN (MD) Port 7 Pin Input 1FD7 XXXX XXXX P1_REG (MH) Port 1 Data Output 1F9D 1111...
Page 482 REGISTERS Table C-2. Register Name, Address, and Reset Status (Continued) Binary Reset Value Register Register Name Mnemonic Addr High T1CONTROL Timer 1 Control 1F78 0000 0000 T2CONTROL Timer 2 Control 1F7C 0000 0000 T1RELOAD Timer 1 Reload 1F72 XXXX XXXX XXXX XXXX TIMER1...
Page 483 8XC196MC, MD, MH USER’S MANUAL AD_COMMAND Address: 1FACH AD_COMMAND Reset State: The A/D command (AD_COMMAND) register selects the A/D channel number to be converted, controls whether the A/D converter starts immediately or with an EPA command, and selects the conversion mode.
Page 484 REGISTERS AD_RESULT (Read) Address: 1FAAH AD_RESULT (Read) Reset State (MC, MD): FFC0H Reset State (MH): 7FC0H The A/D result (AD_RESULT) register consists of two bytes. The high byte contains the eight most- significant bits from the A/D converter. The low byte contains the two least-significant bits from a ten- bit A/D conversion, indicates the A/D channel number that was used for the conversion, and indicates whether a conversion is currently in progress.
Page 485 8XC196MC, MD, MH USER’S MANUAL AD_RESULT (Write) Address: 1FAAH AD_RESULT (Write) Reset State (MC, MD): FFC0H Reset State (MH): 7FC0H The high byte of the A/D result (AD_RESULT) register can be written to set the reference voltage for the A/D threshold-detection modes.
Page 486 REGISTERS AD_TEST Address: 1FAEH AD_TEST Reset State (MC, MD): Reset State (MH): The A/D test (AD_TEST) register specifies adjustments for DC offset errors. — — — OFF1 — OFF0 — — Function Number Mnemonic — Reserved; for compatibility with future devices, write zeros to these bits. OFF1 Offset This bit , along with OFF0 (bit 2) allows you to set the zero offset point.
Page 487 8XC196MC, MD, MH USER’S MANUAL AD_TIME Address: 1FAFH AD_TIME Reset State: The A/D time (AD_TIME) register programs the sample window time and the conversion time for each bit. This register programs the speed at which the A/D can run — not the speed at which it can convert correctly.
Page 488 REGISTERS CCR0 no direct access† CCR0 The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width. LOC1 LOC0 IRC1 IRC0 Function...
Page 489 8XC196MC, MD, MH USER’S MANUAL CCR0 no direct access† CCR0 (Continued) The chip configuration 0 (CCR0) register controls powerdown mode, bus-control signals, and internal memory protection. Three of its bits combine with two bits of CCR1 to control wait states and bus width.
Page 490 REGISTERS CCR1 † no direct access CCR1 The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. IRC2 Function Number...
Page 491 8XC196MC, MD, MH USER’S MANUAL CCR1 † no direct access CCR1 (Continued) The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width.
Page 492 COMPx_CON Address: Table C-3 COMP x _CON Reset State: x = 0–3 (8XC196MC, MH) x = 0–5 (8XC196MD) The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels. x = 0, 2, 4 x = 1, 3, 5 Time Base Select Specifies the reference timer.
Page 493 8XC196MC, MD, MH USER’S MANUAL COMPx_CON Address: Table C-3 COMP x _CON (Continued) Reset State: x = 0–3 (8XC196MC, MH) x = 0–5 (8XC196MD) The EPA compare control (COMP x _CON) registers determine the function of the EPA compare channels.
Page 494 Table C-3 COMP x _TIME Reset State: x = 0–3 (8XC196MC, MH) x = 0–5 (8XC196MD The EPA compare x time (COMP x _TIME) registers are the event-time registers for the EPA compare channels; they are functionally identically to the EPA x _TIME registers. The EPA triggers a compare event when the reference timer matches the value in COMP x _TIME.
Page 495 8XC196MC, MD, MH USER’S MANUAL EPAx_CON Address: Table C-4 EPA x _CON Reset State: x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 496 Table C-4 EPA x _CON (Continued) Reset State: x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels. x = 0, 2, 4...
Page 497 8XC196MC, MD, MH USER’S MANUAL EPAx_CON Address: Table C-4 EPA x _CON (Continued) Reset State: x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) The EPA control (EPA x _CON) registers control the functions of their assigned capture/compare channels.
Page 498 EPA x _TIME Reset State: x = 0–1 (8XC196MH) x = 0–3 (8XC196MC) x = 0–5 (8XC196MD) The EPA time (EPA x _TIME) registers are the event-time registers for the EPA channels. In capture mode, the value of the reference timer is captured in EPA x _TIME when an input transition occurs.
Page 499 8XC196MC, MD, MH USER’S MANUAL FREQ_CNT Address: 1FBAH FREQ_CNT Reset State: (8XC196MD) Read the frequency generator count (FREQ_CNT) register to determine the current value of the down-counter. 8XC196MD Count Function Number Count This register contains the current down-counter value. C-22...
Page 500 REGISTERS FREQ_GEN Address: 1FB8H FREQ_GEN Reset State: (8XC196MD) The frequency (FREQ_GEN) register holds a programmed value that specifies the output frequency. This value is reloaded into the down-counter each time the counter reaches 0. 8XC196MD Output Frequency Function Number Output Frequency Use the following formula to calculate the FREQ value for the desired output frequency and write this value to the frequency register.
Page 501 8XC196MC, MD, MH USER’S MANUAL GEN_CON Address: 1FA0H GEN_CON Reset State: (8XC196MH) The GEN_CON register controls whether an internal reset asserts the external RESET# signal and indicates the source of the most recent reset. 8XC196MH RSTS — — — —...
Page 502 REGISTERS INT_MASK Address: 0008H INT_MASK Reset State: The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests. (The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the low byte of the processor status word (PSW). PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register.
Page 503 SIO 0 and SIO 1 can generate this interrupt. Write to PI_MASK to enable the interrupt sources; read PI_PEND to determine which source caused the interrupt. † On the 8XC196MC device bits 4–3 are reserved. For compatibility with future devices, write zeros to these bits. C-26...
Page 504 REGISTERS INT_PEND Address: 0009H INT_PEND Reset State: When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit. Software can generate an interrupt by setting the corresponding interrupt pending bit. MC, MD COMP2 EPA2...
Page 505 On the 8XC196MD, the waveform generator and the EPA compare channel 5 can generate this interrupt. Write to PI_MASK to enable the interrupt sources; read PI_PEND to determine which source caused the interrupt. On the 8XC196MC, the waveform generator is the sole source for this interrupt.
Page 506 REGISTERS ONES_REG Address: ONES_REG Reset State: FFFFH The two-byte ones register (ONES_REG) is always equal to FFFFH. It is useful as a fixed source of all ones for comparison operations. Function Number 15:0 These bits are always equal to FFFFH. C-29 Get other manuals https://www.bkmanuals.com...
Page 507 8XC196MC, MD, MH USER’S MANUAL Px_DIR Address: Table C-6 P x _DIR Reset State: x = 2, 5 (8XC196MC) x = 2, 5, 7 (8XC196MD) x = 1, 2, 5 (8XC196MH) Each pin of port x can operate in any of the standard I/O modes of operation: complementary output, open-drain output, or high-impedance input.
Page 508 Table C-7 P x _MODE Reset State: x = 2, 5 (8XC196MC) x = 2, 5, 7 (8XC196MD) x = 1, 2, 5 (8XC196MH) Each bit of the port x mode (P x _MODE) register controls whether the corresponding pin functions as a standard I/O port pin or as a special-function signal.
Page 509 8XC196MC, MD, MH USER’S MANUAL Px_MODE Table C-8. Special-function Signals for Ports 1, 2, 5, 6 Port 1 Port 2 Port 2 (8XC196MH) (8XC196MC, MD) (8XC196MH) Special-function Special-function Special-function Signal Signal Signal P1.0 TXD0 P2.0 EPA0/PVER P2.0 EPA0/PVER P1.1 RXD0 P2.1...
Page 510 Table C-9 P x _PIN Reset State: x = 0–5 (8XC196MC, MH) x = 0–5, 7 (8XC196MD) Each bit of the port x pin input (P x _PIN) register reflects the current state of the corresponding pin, regardless of the pin configuration.
Page 511 8XC196MC, MD, MH USER’S MANUAL Px_REG Address: Table C-10 P x _REG Reset State: x = 2–5 (8XC196MC) x = 2–5, 7 (8XC196MD) x = 1–5 (8XC196MH) For an input, set the corresponding port x data output (P x _REG) register bit.
Page 512 1FBCH PI_MASK Reset State: The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM). 8XC196MC — — — — OVRTM2 —...
Page 513 8XC196MC, MD, MH USER’S MANUAL PI_MASK Address: 1FBCH PI_MASK (Continued) Reset State: The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow timer interrupt (OVRTM).
Page 514 (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit. Reading this register clears all the PI_PEND bits. Software can generate an interrupt by setting a PI_PEND bit. 8XC196MC — — —...
Page 515 8XC196MC, MD, MH USER’S MANUAL PI_PEND Address: 1FBEH PI_PEND (Continued) Reset State: When hardware detects a pending peripheral or timer interrupt, it sets the corresponding bit in the interrupt pending (INT_PEND or INT_PEND1) registers and the peripheral interrupt pending (PI_PEND) register. When the vector is taken, the hardware clears the INT_PEND/INT_PEND1 pending bit.
Page 516 The programming pulse width (PPW) register is loaded from the external EPROM (locations 14H and 15H for the 8XC196MC and MD; locations 4014H and 4015H for the 8XC196MH) in auto programming mode. The PPW_VALUE determines the programming pulse width.
Page 517 8XC196MC, MD, MH USER’S MANUAL no direct access The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that...
Page 518 REGISTERS no direct access PSW (Continued) The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.
Page 519 PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts. † On the 8XC196MC device bits 10–12 are reserved. For compatibility with future devices, write zeros to these bits. C-42 Get other manuals https://www.bkmanuals.com...
Page 520 EPA3 (MC, MD) 2050H †† PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts. † On the 8XC196MC device bits 10–12 are reserved. These bits are undefined. C-43 Get other manuals https://www.bkmanuals.com...
Page 521 8XC196MC, MD, MH USER’S MANUAL PWM_COUNT Address: 1FB6H PWM_COUNT Reset State: (read only) The PWM count (PWM_COUNT) register provides the current value of the decremented period counter. PWM Count Value Function Number PWM Count Value This register contains the current value of the decremented period counter.
Page 522 REGISTERS PWM_PERIOD Address: 1FB4H PWM_PERIOD Reset State: The PWM period (PWM_PERIOD) register controls the period of the PWM outputs. It contains a value that determines the number of state counts necessary for incrementing the PWM counter. The value of PWM_PERIOD is loaded into the PWM period count register whenever the count equals zero. PWM Period Function Number...
Page 523 8XC196MC, MD, MH USER’S MANUAL PWMx_CONTROL Address: 1FB0H, 1FB2H PWM x _CONTROL Reset State: x = 0–1 The PWM control (PWM x _CONTROL) register determines the duty cycle of the PWM x channel. A zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in this register causes the PWM to have its maximum duty cycle (99.6% duty cycle).
Page 524 REGISTERS SBUFx_RX Address: 1F80H, 1F88H SBUF x _RX Reset State: x = 0–1 (8XC196MH) The serial port receive buffer x (SBUF x _RX) register contains data received from serial port x . The serial port receiver is buffered and can begin receiving a second data byte before the first byte is read. Data is held in the receive shift register until the last data bit is received, then the data byte is loaded into SBUF x _RX.
Page 525 8XC196MC, MD, MH USER’S MANUAL SBUFx_TX Address: 1F82H, 1F8AH SBUF x _TX Reset State: x = 0–1 (8XC196MH) The serial port transmit buffer x (SBUF x _TX) register contains data that is ready for transmission. In modes 1, 2, and 3, writing to SBUF x _TX starts a transmission. In mode 0, writing to SBUF x _TX starts a transmission only if the receiver is disabled (SP x _CON.3=0).
Page 526 REGISTERS Address: Reset State: XXXXH The system’s stack pointer (SP) can point anywhere in internal or external memory; it must be word aligned and must always be initialized before use. The stack pointer is decremented before a PUSH and incremented after a POP, so the stack pointer should be initialized to two bytes (in 64-Kbyte mode) or four bytes (in 1-Mbyte mode) above the highest stack location.
Page 527 8XC196MC, MD, MH USER’S MANUAL SPx_BAUD Address: 1F84H, 1F8CH SP x _BAUD Reset State: 0000H x = 0–1 (8XC196MH) The serial port baud rate x (SP x _BAUD) register selects the serial port x baud rate and clock source. The most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned integer that determines the baud rate.
Page 528 REGISTERS SPx_CON Address: 1F83H, 1F8BH SP x _CON Reset State: x = 0–1 (8XC196MH) The serial port control (SP x _CON) register selects the communications mode and enables or disables the receiver, parity checking, and nine-bit data transmission. 8XC196MH Function Number Mnemonic See description for bits 0 and 1.
Page 529 8XC196MC, MD, MH USER’S MANUAL SPx_STATUS Address: 1F81H, 1F89H SP x _STATUS Reset State: x = 0–1 (8XC196MH) The serial port status (SP x _STATUS) register contains bits that indicate the status of serial port x . 8XC196MH RPE/RB8 —...
Page 530 REGISTERS T1CONTROL Address: 1F78H T1CONTROL Reset State: The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count rate for timer 1. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 531 8XC196MC, MD, MH USER’S MANUAL T1RELOAD Address: 1F72H T1RELOAD Reset State: XXXXH The timer 1 reload (T1RELOAD) register contains a reinitialization value for timer 1. The value of T1RELOAD is loaded into TIMER1 when timer 1 overflows or underflows and both quadrature clocking and the reload function are enabled (i.e., T1CONTROL.5:0 = 1).
Page 532 REGISTERS T2CONTROL Address: 1F7CH T2CONTROL Reset State: The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count rate for timer 2. Function Number Mnemonic Counter Enable This bit enables or disables the timer. From reset, the timers are disabled and not free running.
Page 533 8XC196MC, MD, MH USER’S MANUAL TIMERx Address: 1F7AH, TIMER x Reset State: 1F7EH x = 1–2 0000H This register contains the value of timer x . This register can be written, allowing timer x to be initialized to a value other than zero.
Page 534 These bits can be programmed, but cannot be erased. WARNING: These bits can be programmed, but can never be erased. Programming these bits makes dynamic failure analysis impossible. For this reason, devices with programmed UPROM bits cannot be returned to Intel for failure analysis. — — —...
Page 535 8XC196MC, MD, MH USER’S MANUAL WATCHDOG Address: WATCHDOG Reset State: Unless it is cleared every 64K state times, the watchdog timer resets the device. To clear the watchdog timer, send “1EH” followed immediately by “E1H” to location 0AH. Clearing this register the first time enables the watchdog with an initial value of 0000H, which is incremented once every state time.
Page 536 REGISTERS WG_COMPx Address: 1FC2H,1FC4H,1FC6H WG_COMP x Reset State: 0000H x = 1–3 The phase compare (WG_COMP x ) register controls the duty cycle of each phase. Write a value to each phase compare register to specify the length of time that the associated outputs will remain asserted.
Page 537 8XC196MC, MD, MH USER’S MANUAL WG_CONTROL Address: 1FCCH WG_CONTROL Reset State (MC, MD): 00C0H Reset State (MH): 8000H The waveform generator control (WG_CONTROL) register controls the operating mode, dead time, and count direction, and enables and disables the counter. —...
Page 538 REGISTERS WG_COUNTER Address: 1FCAH WG_COUNTER Reset State (MC, MD): XXXXH Reset State (MH): 0000H You can read the waveform generator counter (WG_COUNTER) register to determine the current counter value. Counter Value Function Number 15:0 Counter Value This register reflects the current counter value. C-61 Get other manuals https://www.bkmanuals.com...
Page 539 8XC196MC, MD, MH USER’S MANUAL WG_OUTPUT (Port 6) Address: 1FC0H WG_OUTPUT (Port 6) Reset State: 0000H The port 6 output configuration (WG_OUTPUT) register controls port 6 functions. If you are using port 6 for general-purpose outputs, write C0H (for active-high outputs) or 00H (for active-low outputs) to the high byte of WG_OUTPUT and write the desired pin values to the low byte.
Page 540 REGISTERS WG_OUTPUT (Waveform Generator) Address: 1FC0H WG_OUTPUT (Waveform Generator) Reset State: 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6. Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT.
Page 541 8XC196MC, MD, MH USER’S MANUAL WG_OUTPUT (Waveform Generator) Address: 1FC0H WG_OUTPUT (Waveform Generator) (Continued) Reset State: 0000H The waveform generator output configuration (WG_OUTPUT) register controls the configuration of the waveform generator and PWM module pins. Both the waveform generator and the PWM module share pins with port 6.
Page 542 REGISTERS WG_OUTPUT (Waveform Generator) Table C-11. Output Configuration Output Values Output Polarities PH x .2 PH x .1 PH x .0 WG x WG x # WG x WG x # Always Low Always Low WG_EVEN# Always Low WG_ODD Always Low WG_ODD WG_EVEN NOTE: This table assumes active-high outputs (OP1=OP0=1).
Page 543 Enable Outputs This bit enables and disables the outputs. 0 = disable outputs 1 = enable outputs † On the 8XC196MC, MD devices, this bit is reserved. For compatibility with future devices, always write as zero. C-66 Get other manuals https://www.bkmanuals.com...
Page 544 REGISTERS WG_RELOAD Address: 1FC8H WG_RELOAD Reset State: 0000H The waveform generator reload (WG_RELOAD) register and the phase compare registers (WG_COMP x ) control the carrier period and duty cycle. Write a value to the reload register to establish the carrier period. Changing the WG_RELOAD value changes both the carrier period and the duty cycle because the outputs remain asserted for a constant length of time, while the counter takes longer to cycle.
Page 545 8XC196MC, MD, MH USER’S MANUAL Address: 0014H Reset State: The window selection register (WSR) maps sections of RAM into the top of the lower register file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA restores it.
Page 546 REGISTERS Table C-12. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-byte Windows 64-byte Windows 128-byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address EPA2_CON (MC, MD) 1F48H 00E8H 00C8H 00C8H † EPA3_CON (MC, MD) 1F4CH 00ECH...
Page 547 8XC196MC, MD, MH USER’S MANUAL Table C-12. WSR Settings and Direct Addresses for Windowable SFRs (Continued) 32-byte Windows 64-byte Windows 128-byte Windows (00E0–00FFH) (00C0–00FFH) (0080–00FFH) Memory Register Mnemonic Location Direct Direct Direct Address Address Address PWM0_CONTROL 1FB0H 00F0H 00F0H 00B0H...
Page 548 REGISTERS ZERO_REG Address: ZERO_REG Reset State: 0000H The two-byte zero register (ZERO_REG) is always equal to zero. It is useful as a fixed source of the constant zero for comparisons and calculations. Zero Function Number 15:0 Zero This register is always equal to zero. C-71 Get other manuals https://www.bkmanuals.com...
Page 549 Get other manuals https://www.bkmanuals.com...
Page 550 Glossary Get other manuals https://www.bkmanuals.com...
Page 551 Get other manuals https://www.bkmanuals.com...
Page 552 GLOSSARY This glossary defines acronyms, abbreviations, and terms that have special meaning in this man- ual. (Chapter 1 discusses notational conventions and general terminology.) absolute error The maximum difference between corresponding actual and ideal code transitions. Absolute error accounts for all deviations of an actual A/D converter from an ideal converter.
Page 553 8XC196MC, MD, MH USER’S MANUAL CCBs Chip configuration bytes. The chip configuration registers (CCRs) are loaded with the contents of the CCBs after a device reset, unless the device is entering programming modes, in which case the PCCBs are used.
Page 554 GLOSSARY deassert The act of making a signal inactive (disabled). The polarity (high or low) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To deassert RD# is to drive it high; to deassert ALE is to drive it low.
Page 555 8XC196MC, MD, MH USER’S MANUAL full-scale error The difference between the ideal and actual input voltage corresponding to the final (full-scale) code transition of an A/D converter. hold latency The time it takes the microcontroller to assert HLDA# after an external device asserts HOLD#.
Page 556 GLOSSARY 1) Least-significant bit of a byte or least-significant byte of a word. 2) In an A/D converter, the reference voltage divided by 2 , where n is the number of bits to be converted. For a 10-bit converter with a reference voltage of 5.12 volts, one LSB is equal to 5.0 millivolts (5.12 ÷...
Page 557 8XC196MC, MD, MH USER’S MANUAL nonmaskable interrupts Interrupts that cannot be masked (disabled) and cannot be assigned to the PTS for processing. The nonmaskable interrupts are unimplemented opcode, software trap, and NMI. nonvolatile memory Read-only memory that retains its contents when ®...
Page 558 GLOSSARY program memory A partition of memory where instructions can be stored for fetching and execution. protected instruction An instruction that prevents an interrupt from being acknowledged until after the next instruction executes. The protected instructions are DI, EI, DPTS, EPTS, POPA, POPF, PUSHA, and PUSHF.
Page 559 8XC196MC, MD, MH USER’S MANUAL Pulse-width modulated (outputs). The 8XC196Mx devices have several options for producing PWM outputs: the generic pulse-width modulator modules, the waveform generator, and the EPA with or without the PTS. The 8XC196MD also has a frequency generator that produces PWM outputs.
Page 560 GLOSSARY sample time The period of time that the sample window is open. (That is, the length of time that the input channel is actually connected to the sample capacitor.) sample time uncertainty The variation in the sample time. sample window The period of time that begins when the sample capacitor is attached to a selected channel of an A/D converter and ends when the sample capacitor is...
Page 561 8XC196MC, MD, MH USER’S MANUAL special interrupt Any of the three nonmaskable interrupts (unimple- mented opcode, software trap, or NMI). special-purpose memory A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and several reserved locations.
Page 562 GLOSSARY transfer function errors Errors inherent in an analog-to-digital conversion process: quantizing error, zero-offset error, full-scale error, differential nonlinearity, and nonlinearity. Errors that are hardware-dependent, rather than being inherent in the process itself, include feedthrough, repeatability, channel-to-channel matching, off- isolation, and V rejection errors.
Page 563 Get other manuals https://www.bkmanuals.com...
Page 564 Index Get other manuals https://www.bkmanuals.com...
Page 565 Get other manuals https://www.bkmanuals.com...
Page 566 INDEX #, defined, 1-3, A-1 transfer function, 12-15–12-18 16-bit data bus zero-offset adjustment, 12-3, 12-5 read cycles, 15-14 zero-offset error, 12-16 timing diagram, 15-15 See also port 0 write cycles, 15-14 A/D result register (read), 12-9, C-7 8-bit data bus A/D result register (write), 12-6, C-8 read cycles, 15-16 A/D scan mode‚...
Page 567 8XC196MC, MD, MH USER’S MANUAL AND instruction, A-2, A-8, A-41, A-42, A-48, standard, 15-22–15-24 A-53 write strobe, 15-25–15-26 ANDB instruction, A-2, A-8, A-9, A-42, A-43, Bus-control signals, 15-21 A-48, A-53 Bus-width modes ANGND, 12-5, 13-1, B-14 16-bit data bus, 15-14...
Page 568 INDEX Clock pin reset status, B-23, B-25 external, 13-7 programming, 16-1–16-33 generator, 2-7, 13-7, 13-8 reset, 13-8, 13-9, 13-10, 13-11, 13-12 internal, and idle mode, 14-4, 14-5 DI instruction, A-3, A-12, A-46, A-51, A-57 phases, internal, 2-8 Digital-to-analog converter, 10-10 CLR instruction, A-2, A-10, A-41, A-47, A-52 DIR bit, 7-2, 7-6 CLRB instruction, A-2, A-11, A-41, A-47, A-52...
Page 569 8XC196MC, MD, MH USER’S MANUAL re-enabling the compare event, 11-20, 11-22 A/D conversion time, 12-7 reloading the waveform generator, 11-20, A/D error, 12-11 11-23, C-16 A/D sample time, 12-7 resetting the timer in compare mode, 11-21 A/D series resistance, 12-10...
Page 570 INDEX Hypertext manuals and datasheets, downloading, Interrupt pending register, 5-21, C-27 Interrupts, 5-1–5-58 1-10 controller, 2-6, 5-1 end-of-PTS, 5-25 inhibiting, 5-9 Idle mode, 2-11, 13-13, 14-4–14-5 latency, 5-9–5-11 entering, 14-5 calculating, 5-10 pin status, B-23, B-25 priorities, 5-4, 5-5 timeout control, 11-7 modifying, 5-18–5-19 IDLPD instruction, A-2, A-16, A-46, A-51, A-57 procedures, PLM-96, 3-11...
Page 571 8XC196MC, MD, MH USER’S MANUAL JVT instruction, A-3, A-5, A-23, A-45, A-50, A-56 Mode 4, SIO, 7-6 Modified quick-pulse algorithm, 16-9 MUL instruction, A-25, A-46, A-48, A-53 MULB instruction, A-25, A-46, A-48, A-53 Latency‚ See bus-hold protocol‚ interrupts Multiprocessor communications...
Page 572 INDEX ORB instruction, A-2, A-28, A-43, A-48, A-53 P6_REG, C-69 Oscillator P7.7:0, B-19 and powerdown mode, 14-5 PACT#, B-19 external crystal, 13-6 PALE#, 16-8, 16-10, 16-11, B-19 on-chip, 13-5 Parameters, passing to subroutines, 3-10 OTPROM Parity, 7-7, 7-8, 7-9 controlling access to internal memory, PBUS, 16-12 16-3–16-6 PBUS15:0, B-19...
Page 573 8XC196MC, MD, MH USER’S MANUAL SFRs, 6-6, 14-3 enabling, 14-5 entering, 14-6 Port 3, B-18 addressing, 6-14 exiting, 14-6 idle, powerdown, reset status, B-23, B-25 with EXTINT, 14-7–14-10 operation, 6-15–6-16 with RESET#, 14-6 overview, 6-1 with V , 14-6 pin configuration, 6-14...
Page 574 INDEX instructions, A-51, A-57 interrupt latency, 5-11 Quadrature clocking, 11-7 interrupt processing flow, 5-2 Quick reference guides, ordering, 1-8 routine, defined, 5-1 serial I/O modes, 5-37–5-58 single transfer mode, 5-27 RALU, 2-4–2-6 synchronous serial I/O receive mode, RD#, B-20 5-47–5-50 considerations, 6-13 synchronous serial I/O transmit mode, idle, powerdown, reset status, B-23, B-25...
Page 575 8XC196MC, MD, MH USER’S MANUAL FREQ_CNT, 8-4, C-22 SP1_CON, 7-4 SP1_STATUS, 7-4 FREQ_GEN, 8-3, C-23 GEN_CON, 13-9, C-24 SPx_BAUD, 7-12, C-50 grouped by modules, C-1 SPx_CON, 7-10, C-51 INT_MASK, 5-15, C-25 SPx_STAUS, 7-15, C-52 INT_MASK1, 5-16, 7-2, C-26 T1CONTROL, 11-16, C-53...
Page 576 INDEX RST instruction, 3-11, 13-9, 13-12, A-3, A-31, SHRL instruction, A-3, A-36, A-41, A-51, A-57 A-46, A-51, A-57 Signals Run-time programming, 16-32–16-33 configuring for external memory interfacing, code example, 16-33 15-5 RXD, B-20 default conditions, B-23, B-25 and SIO port mode 0, 7-5, 7-7 descriptions, B-13–B-22 and SIO port modes 1, 2, and 3, 7-7 external memory, 15-1...
Page 577 8XC196MC, MD, MH USER’S MANUAL SJMP instruction, A-2, A-36, A-41, A-47, A-49, Subroutines linking, 3-10 A-55 SKIP instruction, A-2, A-36, A-41, A-51, A-57 nested, 4-10 Slave programming mode, 16-15–16-24 Symbols address/command decoder routine, 16-19, signal status, B-23 16-20 System bus timing, 15-32 algorithm, 16-19–16-24...
Page 578 INDEX Timing diagrams and duty cycle, 9-19 16-bit data bus, 15-15 generator circuitry, 9-5 8-bit data bus, 15-17 design considerations, 9-19, 9-20 BUSWIDTH, 15-12 EXTINT interrupts and protection circuitry, READY, 15-19 9-21 system bus timing, 15-32 interrupts, 9-20 Timing requirements operating modes, 9-7, 9-11 BUSWIDTH, 15-13 center-aligned, 9-8, 9-9, 9-10...
Page 579 8XC196MC, MD, MH USER’S MANUAL WSR values and direct addresses, 4-15 WORD, defined, 3-2 World Wide Web, 1-11 WR#, B-22 idle, powerdown, reset status, B-23, B-25 WRH#, B-22 Write cycles 16-bit data bus, 15-14 8-bit data bus, 15-16 Write strobe mode...

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