Intel 8XC196K Series User Manual page 144

Table of Contents

This pin is not implemented on 8XC196J x and 87C196CA devices.

This pin is not implemented on 8XC196J x devices.

P5.4/SLPINT is not implemented on 8XC196J x devices. P5.4 is

implemented on the 87C196CA as a low-speed input/output pin (but it is not

multiplexed with SLPINT).

Table 6-5 lists the registers associated with the bidirectional ports. Each port has three control reg-

isters (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN regis-

ter is a status register that returns the logic level present on the pins; it can only be read. The

registers for the standard ports are byte-addressable and can be windowed. The port 5 registers

must be accessed using 16-bit addressing and cannot be windowed. "Bidirectional Port Consid-

erations" on page 6-12 discusses special considerations for reading P2_REG.7 and P6_REG.7:4.

Table 6-5. Bidirectional Port Control and Status Registers

Table 6-4. Bidirectional Port Pins (Continued)

Special-function

Port x Direction

Each bit of P x _DIR controls the direction of the corresponding pin.

0 =complementary output (output only)

1 =input or open-drain output (input, output, or bidirectional)

Open-drain outputs require external pull-ups.

Bus controller

Bus controller

Bus controller

Bus controller