ST STM32F40 Series Reference Manual page 1415

Revision history
Table 240. Document revision history
Date
19-Oct-2012
1415/1422
Version
General purpose timers (TIM2 to TIM5)
Removed all references to "repetition counter".
Added Figure 119: General-purpose timer block
Updated 16-bit prescaler range in
features.
External clock mode 2 ETR restricted to TIM2 to TIM4 in
Section 15.3.3: Clock selection
mode.
Updated Section 15.3.9: PWM mode
the OCxREF signal on an external
Updated Figure 159: Master/Slave timer example
ITR0.
Updated read and write access to registers in
TIM5 registerss.
Restored bits 15 to 8 of TIMx_SMCR as well as
internal trigger connection
Removed note 1 related to OC1M bits in
capture/compare register 1
Updated TIMx_CCER bit description for TIM2 to TIM5 in
Section 15.4.9: TIMx capture/compare enable register
(TIMx_CCER).
2
(continued)
General purpose timers (TIM9 to TIM14)
Updated 16-bit prescaler range in
features and
features.
Updated Figure 166: General-purpose timer block diagram
(TIM10/11/13/14))
Added register access in
and Section 16.6: TIM10/11/13/14
Basic timers (TIM6 and TIM7)
Removed all references to "repetition counter".
Updated 16-bit prescaler range in
features.
HASH:
Updated Section 22.3.1: Duration of the
RNG:
Updated Section 21.1: RNG
Doc ID 018909 Rev 4
Changes
Section 15.2: TIM2 to TIM5 main
and Section 15.3.6: PWM input
event.
in Section
(TIMx_CCR1).
Section 16.2.1: TIM9/TIM12 main
Section 16.3: TIM10/TIM11 and TIM13/TIM14 main
to remove TRGO trigger controller output.
Section 16.5: TIM9 and TIM12 registers
registers.
Section 17.2: TIM6&TIM7 main
introduction.
RM0090
diagram.
and Section 15.3.11: Clearing
to change ITR1 to
Section 15.4: TIM2 to
Table 76: TIMx
14.4.3.
Section 15.4.13: TIMx
processing.