ST STM32F40 Series Reference Manual page 1418

RM0090
Table 240. Document revision history
Date
19-Oct-2012
Version
FSMC:
Updated step b) in
transactions.
Updated Table 196: FSMC_BTRx bit
FSMC_BTRx bit
Changed Clock divide ration min in
NAND/PC Card access
Updated case of synchronous accesses in
Flash/PSRAM
Changed minimum value for ADDSET to 0 in
Table 207,
Move note from
Mode1 read
accesses to
Updated Section : WAIT management in asynchronous
Added register access in
registers and
memories and
Removed caution note in
signalss.
2
(continued)
Updated Table 218: 16-bit PC Card.
Updated step 3 in
Updated Figure 424: Access to non 'CE don't care' NAND-Flash
note below in
Updated access to I/O Space in
Card/CompactFlash
signals and access
Section : SRAM/NOR-Flash chip-select timing registers 1..4
(FSMC_BTR1..4)). Changed bits 16 to 19 to BUSTURN in
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)
DEBUG:
Updated Section 33.4.3: Internal pull-up and pull-down on JTAG
pins.
Electronic signature
Updated Section 34: Device electronic signature
Updated REV_ID[15:0] to add revision Z in
device ID code.
Updated address and example in
Doc ID 018909 Rev 4
Changes
Section 32.3.1: Supported memories and
fields.
parameters.
controller.
Table 209, and Table 210.
Figure 406: Mode1 write accesses
accesses. Move note from
Figure 407: ModeA read
Section 32.5.6: NOR/PSRAM control
Section 32.6.2: NAND Flash / PC Card supported
transactions.
Section 32.6.1: External memory interface
Section 32.6.4: NAND Flash
Section 32.6.5: NAND Flash pre-wait
Section 32.6.7: PC
operationss. Updated
type. Updated BUSTURN bit definition in
Section 34.2: Flash
Revision history
fields, and Table 204:
Table 215: Programmable
Section 32.5: NOR
Table 203, Table
and Figure 405:
Figure 408: ModeA write
accesses.
accesses.
operations.
functionality.
Table 220: 16-bit PC-Card
Section :
introduction.
Section 33.6.1: MCU
size.
1418/1422
206,
and