ST STM32F40 Series Reference Manual page 1417

Revision history
Table 240. Document revision history
Date
19-Oct-2012
1417/1422
Version
SDIO:
Updated value and description for bits [45:40] and [7:1] in
R4 response. Updated value at bits [45:40] in
response.
CAN:
Updated Figure 224: Dual CAN block
Modified definition of CAN2SB bits in
register (CAN_FMR).
Added register access in
ETHERNET:
Updated standard for precision networked clock synchronization in
Section 29.1: Ethernet introduction
features.
Updated CR bit definition in
register (ETH_MACMIIAR).
Replace RTPR by PM bit in
USB OTG FS
2
(continued)
Updated remote wakeup signaling bit and the resume
interrupt in
Added peripheral register access in
and status
Updated INEPTXSA description in OTG_FS_DIEPTXFx.
Changed PHYSEL from bit 7 to bit 6 of the OTG_FS_GUSBCFG
register.
USB OTG HS
Updated remote wakeup signaling bit and the resume
interrupt in
Added peripheral register access in
and status
Updated INEPTXSA description in OTG_HS_DIEPTXFx.
Updated FSLSPCS for LS host mode, added PHYSEL in
OTG_HS host configuration register
Renamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of
the OTG_HS_GUSBCFG register.
Updated OTG_HS_DIEPEACHMSK1 and
OTG_HS_DOEPEACHMSK1 reset values.
Doc ID 018909 Rev 4
Changes
Section 24.9: CAN registers
Section : Ethernet MAC MII address
Table 167: Source address
Section : Suspended state
registerss.
Section : Suspended state
registers.
Table 154:
Table 156: R5
diagram.
Section : CAN filter master
and Section 29.2.1: MAC core
filtering.
.
Section 30.16: OTG_FS control
.
Section 31.12: OTG_HS control
Section :
(OTG_HS_HCFG).
RM0090