ST STM32F40 Series Reference Manual page 1420

RM0090
Table 240. Document revision history
Date
19-Feb-2013
Version
Updated Section 2.3.1: Embedded
Updated Figure 1: System architecture for STM32F405xx/07xx and
STM32F415xx/17xx
STM32F42xxx and STM32F43xxx
Memory mapping vs. Boot mode/physical
Sequential 32-bit instruction
Number of wait states according to CPU clock (HCLK) frequency
Table 8: Program/erase
PWR:
Updated Figure 7: Power supply
Updated Section 5.1.3: Voltage
Added ADCDC1 bit in
(PWR_CR) for STM32F42xxx and
SYSCFG:
Added ADCxDC2 bit in
configuration register (SYSCFG_PMC) for STM32F42xxx and
4
STM32F43xxx.
ADC:
Updated Section 11.9.3: Interleaved
trigger mode, and
alternate trigger mode
Updated Section : Temperature sensor, VREFINT and VBAT internal
channels, Section 11.10: Temperature
Battery charge
RTC:
Updated BKP[31:0] bit description in
registers (RTC_BKPxR).
I2C:
Updated Section 25.3.5: Programmable noise
Doc ID 018909 Rev 4
Changes
SRAM.
devices, and Figure 2: System architecture for
devices. Updated
execution. removed note 1 from
parallelism.
overview.
regulator.
Section 5.4.2: PWR power control register
STM32F43xxx.
Section 8.2.3: SYSCFG peripheral mode
mode,
Section 11.9.6: Combined regular simultaneous +
to describe case of interrupted conversion.
sensor, and
monitoring.
Section 23.6.20: RTC backup
Revision history
Table 4:
remap. Updated Figure 4:
Table 7:
and
Section 11.9.4: Alternate
Section 11.11:
filter.
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