ST STM32F40 Series Reference Manual page 1416

RM0090
Table 240. Document revision history
Date
19-Oct-2012
Version
RTC:
Updated Figure 222: RTC block
Added formula to compute
prescalers
Updated Section 23.3.9: RTC reference clock
Updated Section : RTC register write
Added RTC_SSR shadow register in
calendar.
Updated description of DC[4:0] bits in
calibration register
Renamed RTC_BKxR into RTC_BKPxR in
map and reset
Added power-on reset value and changed reset value to system
reset value in
(RTC_SSR).
Updated definition of ALARMOUTTYPE in
tamper and alternate function configuration register
I2C:
Modified Section 25.3.8: DMA
Updated bit 14 description in
register 1 (I2C_OAR1)).
2
Updated definition of PE bit and note related to SWRST bit; moved
(continued)
note related to STOP bit to the whole register in
Control register 1
USART:
Section 26.6.6: Control register 3
related to UART5 in DMAT and DMAR description.
TTable 116: Error calculation for programmed baud rates at
Updated
fPCLK = 42 MHz or fPCLK = 84 Hz, oversampling by 16
Table 117: Error calculation for programmed baud rates at fPCLK =
42 MHz or fPCLK = 84 MHz, oversampling by
SPI/I2S:
Updated Section 27.1: SPI
Changed I2S simplex communication/mode to half-duplex
communication/mode. Updated flags in reception/transmission
modes in Section 27.2.2: I2S
Table 126: I2S interrupt
Added register access in
Updated ERRIE definition in
(SPI_CR2).
Renamed TIFRFE to FRE and definition updated in
SPI status register
Doc ID 018909 Rev 4
Changes
diagram.
f
ck_apre
.
(RTC_CALIBR).
values.
Section 23.6.11: RTC sub second register
requests.
Section 25.6.3: I2C Own address
(I2C_CR1).
(USART_CR3)): removed notes
introduction.
features. Added Frame error flag in
requests.
Section 27.5: SPI and I2S
Section 27.5.2: SPI control register 2
(SPI_SR).
Revision history
in Section 23.3.1: Clock and
detection.
protection.
Section 23.3.6: Reading the
Section 23.6.7: RTC
Table 99: RTC register
Section 23.6.17: RTC
(RTC_TAFCR).
Section 25.6.1: I2C
and
8.
registers.
Section 27.5.3:
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