Hash Context Swap Registers (Hash_Csrx) - ST STM32F207 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0033
21.4.7

HASH context swap registers (HASH_CSRx)

Address offset: 0x0F8 to 0x1C0
For HASH_CSR0 register: Reset value is 0x0000 0002.
For others registers: Reset value is 0x0000 0000
These registers contain the complete internal register states of the hash processor, and are
useful when a context swap has to be done because a high-priority task has to use the hash
processor while it is already in use by another task.
When such an event occurs, the HASH_CSRx registers have to be read and the read
values have to be saved somewhere in the system memory space. Then the hash
processor can be used by the preemptive task, and when hash computation is finished, the
saved context can be read from memory and written back into these HASH_CSRx registers.
HASH_CSRx
Address offset: 0x0F8 to 0x1C0
31
30
29
rw
rw
rw
15
14
13
rw
rw
rw
28
27
26
25
rw
rw
rw
rw
12
11
10
9
rw
rw
rw
rw
24
23
22
CSx
rw
rw
rw
8
7
6
CSx
rw
rw
rw
RM0033 Rev 9
Hash processor (HASH)
21
20
19
18
rw
rw
rw
rw
5
4
3
2
rw
rw
rw
rw
17
16
rw
rw
1
0
rw
rw
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