Hash Interrupt Enable Register (Hash_Imr) - ST STM32F205 series Reference Manual

RM0033
31 30 29
r r r
15 14 13
r r r
HASH_HR4
Address offset: 0x1C
31 30 29
r r r
15 14 13
r r r
Note: When starting a digest computation for a new bit stream (by writing the INIT bit to 1), these
registers assume their reset values.
21.4.5

HASH interrupt enable register (HASH_IMR)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
15 14 13
28 27 26 25
r r r r
12 11 10 9
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
28 27 26 25
12 11 10 9
Reserved
Bits 31:2 Reserved, forced by hardware to 0.
Bit 1 DCIE: Digest calculation completion interrupt enable
0: Digest calculation completion interrupt disabled
1: Digest calculation completion interrupt enabled.
Bit 0 DINIE: Data input interrupt enable
0: Data input interrupt disabled
1: Data input interrupt enabled
24 23 22
H3
r r r
8 7 6
H3
r r r
24 23 22
H4
r r r
8 7 6
H4
r r r
24 23 22
Reserved
8 7 6
RM0033 Rev 8
Hash processor (HASH)
21 20 19 18
r r r r
5 4 3 2
r r r r
21 20 19 18
r r r r
5 4 3 2
r r r r
21 20 19 18
5 4 3 2
17 16
r r
1 0
r r
17 16
r r
1 0
r r
17 16
1 0
DCIE DINIE
rw rw
565/1378
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