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Real-time clock (RTC)
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 CALP: Increase frequency of RTC by 488.5 ppm
Bit 14 CALW8: Use an 8-second calibration cycle period
Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to
Bit 13 CALW16: Use a 16-second calibration cycle period
Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to
Bit 12 LPCAL: Calibration low-power mode
Bits 11:9 Reserved, must be kept at reset value.
Bits 8:0 CALM[8:0]: Calibration minus
32.6.10
RTC shift control register (RTC_SHIFTR)
This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x2C
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
ADD1S
Res.
Res.
Res.
w
15
14
13
Res.
w
w
1020/1454
0: No RTCCLK pulses are added.
1: One RTCCLK pulse is effectively inserted every 2
488.5 ppm).
This feature is intended to be used in conjunction with CALM, which lowers the frequency of
the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of
RTCCLK pulses added during a 32-second window is calculated as follows: (512 × CALP) -
CALM.
Refer to
Section 32.3.14: RTC smooth digital
When CALW8 is set to 1, the 8-second calibration cycle period is selected.
digital
calibration.
When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must
not be set to 1 if CALW8 = 1.
calibration.
0: Calibration window is 2
be set only when less than 32s calibration window is required.
1: Calibration window is 2
consumption mode.
The frequency of the calendar is reduced by masking CALM out of 2
seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar
with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in conjunction with
CALP. See
Section 32.3.14: RTC smooth digital calibration on page
999.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
w
w
w
w
calibration.
20
RTCCLK, which is a high-consumption mode. This mode should
20
ck_apre, which is the required configuration for ultra-low
24
23
22
Res.
Res.
Res.
8
7
6
SUBFS[14:0]
w
w
w
RM0453 Rev 2
11
pulses (frequency increased by
Section 32.3.14: RTC smooth
Section 32.3.14: RTC smooth digital
20
RTCCLK pulses (32
1004.
RTC register
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
w
w
w
w
RM0453
17
16
Res.
Res.
1
0
w
w
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