ST STM32WL55JC Reference Manual page 1013

RM0453
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 RECALPF: Recalibration pending Flag
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:10 BCDU[2:0]: BCD update (BIN = 10 or 11)
Bits 9:8 BIN[1:0]: Binary mode
Bit 7 INIT: Initialization mode
Bit 6 INITF: Initialization flag
Bit 5 RSF: Registers synchronization flag
Bit 4 INITS: Initialization status flag
The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR
register, indicating that the RTC_CALR register is blocked. When the new calibration settings
are taken into account, this bit returns to 0. Refer to
In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or
11), the calendar second is incremented using the SSR Least Significant Bits.
0x0: 1s calendar increment is generated each time SS[7:0] = 0
0x1: 1s calendar increment is generated each time SS[8:0] = 0
0x2: 1s calendar increment is generated each time SS[9:0] = 0
0x3: 1s calendar increment is generated each time SS[10:0] = 0
0x4: 1s calendar increment is generated each time SS[11:0] = 0
0x5: 1s calendar increment is generated each time SS[12:0] = 0
0x6: 1s calendar increment is generated each time SS[13:0] = 0
0x7: 1s calendar increment is generated each time SS[14:0] = 0
00: Free running BCD calendar mode (Binary mode disabled).
01: Free running Binary mode (BCD mode disabled)
10: Free running BCD calendar and Binary modes
11: Free running BCD calendar and Binary modes
0: Free running mode
1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and
prescaler register (RTC_PRER), plus BIN and BCDU fields. Counters are stopped and start
counting from the new value when INIT is reset.
When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler
registers can be updated.
0: Calendar registers update is not allowed
1: Calendar registers update is allowed
This bit is set by hardware each time the calendar registers are copied into the shadow
registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization
mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register
mode (BYPSHAD = 1). This bit can also be cleared by software.
It is cleared either by software or by hardware in initialization mode.
0: Calendar shadow registers not yet synchronized
1: Calendar shadow registers synchronized
This bit is set by hardware when the calendar year field is different from 0 (Backup domain
reset state).
0: Calendar has not been initialized
1: Calendar has been initialized
RM0453 Rev 2
Real-time clock (RTC)
Re-calibration on-the-fly.
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