ST STM32WL55JC Reference Manual page 1021

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
Bit 31 ADD1S: Add one second
Bits 30:15 Reserved, must be kept at reset value.
Bits 14:0 SUBFS[14:0]: Subtract a fraction of a second
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be
32.6.11
RTC timestamp time register (RTC_TSTR)
The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when
TSF bit is reset.
Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
MNT[2:0]
r
r
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 PM: AM/PM notation
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF = 1, in RTC_ICSR).
This function is intended to be used with SUBFS (see description below) in order to
effectively add a fraction of a second to the clock in an atomic operation.
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF = 1, in RTC_ICSR).
The value which is written to SUBFS is added to the synchronous prescaler counter. Since
this counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))).
In mixed BCD-binary mode (BIN=10 or 11), the SUBFS[14:BCDU+8] must be written with 0.
sure that the shadow registers have been updated with the shifted time.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
MNU[3:0]
r
r
r
r
0: AM or 24-hour format
1: PM
24
23
22
Res.
Res.
PM
r
8
7
6
Res.
ST[2:0]
r
r
RM0453 Rev 2
Real-time clock (RTC)
21
20
19
18
HT[1:0]
HU[3:0]
r
r
r
r
5
4
3
2
SU[3:0]
r
r
r
r
17
16
r
r
1
0
r
r
1021/1454
1049

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