ST STM32WL55JC Reference Manual page 1040

Tamper and backup registers (TAMP)
Bit 2 TAMP3E: Tamper detection on TAMP_IN3 enable
Bit 1 TAMP2E: Tamper detection on TAMP_IN2 enable
Bit 0 TAMP1E: Tamper detection on TAMP_IN1 enable
33.6.2 TAMP control register 2 (TAMP_CR2)
Address offset: 0x04
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 TAMP3TRG: Active level for tamper 3 input
Bit 25 TAMP2TRG: Active level for tamper 2 input
Bit 24 TAMP1TRG: Active level for tamper 1 input
1040/1454
0: Tamper detection on TAMP_IN3 is disabled.
1: Tamper detection on TAMP_IN3 is enabled.
0: Tamper detection on TAMP_IN2 is disabled.
1: Tamper detection on TAMP_IN2 is enabled.
0: Tamper detection on TAMP_IN1 is disabled.
1: Tamper detection on TAMP_IN1 is enabled.
28 27 26 25
TAMP3 TAMP2
Res.
TRG TRG
rw rw
12 11 10 9
Res. Res. Res.
0: If TAMPFLT ≠ 00 Tamper 3 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 3 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 3 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 3 input falling edge and low level triggers a tamper detection
event.
0: If TAMPFLT ≠ 00 Tamper 2 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 2 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection
event.
0: If TAMPFLT ≠ 00 Tamper 1 input staying low triggers a tamper detection event.
If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection
event.
1: If TAMPFLT ≠ 00 Tamper 1 input staying high triggers a tamper detection event.
If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection
event.
24 23 22
TAMP1 BK
Res.
TRG ERASE
w
rw
8 7 6
Res. Res. Res.
RM0453 Rev 2
21 20 19 18
TAMP3
Res. Res. Res.
MSK
rw
5 4 3 2
TAMP3
Res. Res. Res.
NOER
rw
RM0453
17 16
TAMP2 TAMP1
MSK MSK
rw rw
1 0
TAMP2 TAMP1
NOER NOER
rw rw