ST STM32WL55JC Reference Manual page 1022

Real-time clock (RTC)
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.
32.6.12 RTC timestamp date register (RTC_TSDR)
The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when
TSF bit is reset.
Address offset: 0x34
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
WDU[2:0]
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:13 WDU[2:0]: Week day units
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format
32.6.13 RTC timestamp sub second register (RTC_TSSSR)
The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when
the TSF bit is reset.
Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
r r r
15 14 13
r r r
1022/1454
28 27 26 25
Res. Res. Res.
12 11 10 9
MT MU[3:0]
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
24 23 22
Res. Res. Res.
8 7 6
Res. Res.
r
24 23 22
SS[31:16]
r r r
8 7 6
SS[15:0]
r r r
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
DT[1:0]
r r r r
21 20 19 18
r r r r
5 4 3 2
r r r r
RM0453
17 16
Res. Res.
1 0
DU[3:0]
r r
17 16
r r
1 0
r r