ST STM32WL55JC Reference Manual page 999

RM0453
32.3.9 RTC initialization and configuration
RTC Binary, BCD or Mixed mode
By default the RTC is in BCD mode (BIN = 00 in the RTC_ICSR register): the RTC_SSR
register contains the sub-second field SS[15:0], clocked by ck_apre, allowing the generation
of a 1 Hz clock to update the calendar registers in BCD format (RTC_TR and RTC_DR).
When the RTC is configured in binary mode (BIN = 01 in the RTC_ICSR register): the
RTC_SSR register contains the binary counter SS[31:0], clocked by ck_apre. The calendar
registers in BCD format (RTC_TR and RTC_DR) are not used.
When the RTC is configured in mixed mode (BIN = 10 or 11 in the RTC_ICSR register): the
RTC_SSR register contains the binary counter SS[31:0], clocked by ck_apre. The calendar
is updated (1 second increment) each time the SSR[BCDU+7:0] reaches 0.
RTC register access
The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC
register accesses except on read accesses to calendar shadow registers when BYPSHAD
= 0.
RTC register write protection
After system reset, the RTC registers are protected against parasitic write access by the
DBP bit in the power control peripheral (refer to the PWR power control section). DBP bit
must be set in order to enable RTC registers write access.
After Backup domain reset, some of the RTC registers are write-protected: RTC_TR,
RTC_DR, RTC_PRER, RTC_CALR, RTC_SHIFTR, the bits INIT, BIN and BCDU in
RTC_ICSR and the bits FMT, SUB1H, ADD1H, REFCKON in RTC_CR.
The following steps are required to unlock the write protection on the protected RTC
registers.
1. Write 0xCA into the RTC_WPR register.
2. Write 0x53 into the RTC_WPR register.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.
Calendar initialization and configuration
To program the initial time and date calendar values, including the time format and the
prescaler configuration, the following sequence is required:
1. Set INIT bit to 1 in the RTC_ICSR register to enter initialization mode. In this mode, the
calendar counter is stopped and its value can be updated.
2. Poll INITF bit of in the RTC_ICSR register. The initialization phase mode is entered
when INITF is set to 1.
RM0453 Rev 2
Real-time clock (RTC)
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