ST STM32WL55JC Reference Manual page 1030

Real-time clock (RTC)
32.6.21 RTC alarm A binary mode register (RTC_ALRABINR)
This register can be written only when ALRAE is reset in RTC_CR register, or in initialization
mode.
Address offset: 0x70
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
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15 14 13
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Bits 31:0 SS[31:0]: Synchronous counter alarm value in Binary mode
32.6.22 RTC alarm B binary mode register (RTC_ALRBBINR)
This register can be written only when ALRBE is reset in RTC_CR register, or in initialization
mode.
Address offset: 0x74
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
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15 14 13
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Bits 31:0 SS[31:0]: Synchronous counter alarm value in Binary mode
1030/1454
28 27 26 25
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12 11 10 9
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This value is compared with the contents of the synchronous counter to determine if Alarm A
is to be activated. Only bits 0 up MASKSS-1 are compared.
SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMASSRR, and so can also be read or
written through RTC_ALRMASSR.
28 27 26 25
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12 11 10 9
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This value is compared with the contents of the synchronous counter to determine if Alarm
Bis to be activated. Only bits 0 up MASKSS-1 are compared.
SS[14:0] is the mirror of SS[14:0] in the RTC_ALRMBSSRR, and so can also be read or
written through RTC_ALRMBSSR.
24 23 22
SS[31:16]
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8 7 6
SS[15:0]
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24 23 22
SS[31:16]
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8 7 6
SS[15:0]
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RM0453 Rev 2
21 20 19 18
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5 4 3 2
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21 20 19 18
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5 4 3 2
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RM0453
17 16
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1 0
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17 16
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1 0
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