Table 206. Wwdg Register Map And Reset Values - ST STM32WL55JC Reference Manual

Real-time clock (RTC)
32.3.2 RTC pins and internal signals
Pin name
RTC_TS
RTC_REFIN
RTC_OUT1
RTC_OUT2
RTC_OUT1 and RTC_OUT2 select one of the following two outputs:
–
–
ALARM is enabled by configuring the OSEL[1:0] bits in the RTC_CR register which select
the alarm A, alarm B or wakeup outputs. TAMP is enabled by setting the TAMPOE bit in the
RTC_CR register which selects the tamper event outputs.
Internal signal name
rtc_ker_ck
rtc_pclk
rtc_its
rtc_tamp_evt
rtc_it
rtc_alra_trg
rtc_alrb_trg
rtc_wut_trg
rtc_calovf
The RTC kernel clock is usually the LSE at 32.768 kHz although it is possible to select other
clock sources in the RCC (refer to RCC for more details). Some functions are not available
in some low-power modes or V
Section 32.4: RTC low-power modes
992/1454
Table 207. RTC input/output pins
CALIB: 512 Hz or 1 Hz clock output (with an LSE frequency of 32.768 kHz). This
output is enabled by setting the COE bit in the RTC_CR register.
TAMPALRM: This output is the OR between TAMP and ALARM outputs.
Table 208. RTC internal input/output signals
Signal type
Input
Input
Input
Input
Output
Output
Output
Output
Output
Signal type
Input RTC timestamp input
Input RTC 50 or 60 Hz reference clock input
Output RTC output 1
Output RTC output 2
RTC kernel clock, also named RTCCLK in this document
RTC APB clock
RTC internal timestamp event
Tamper event (internal or external) detected in TAMP
peripheral
RTC interrupts (refer to
details)
RTC alarm A event detection trigger
RTC alarm B event detection trigger
RTC wakeup timer event detection trigger
RTC calendar overflow: this signal is generated when the
RTC calendar reaches its maximum value, on the 31
December 99, at 23:59:59. The calendar is then frozen and
cannot overflow.
when the selected clock is not LSE. Refer to
BAT
for more details.
RM0453 Rev 2
Description
Description
Section 32.5: RTC interrupts
RM0453
for
st
of