ST STM32WL55JC Reference Manual page 1027

RM0453
32.6.18 RTC status register (RTC_SR)
Address offset: 0x50
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 SSRUF: SSR underflow flag
Bit 5 ITSF: Internal timestamp flag
Bit 4 TSOVF: Timestamp overflow flag
Bit 3 TSF: Timestamp flag
Bit 2 WUTF: Wakeup timer flag
Bit 1 ALRBF: Alarm B flag
Bit 0 ALRAF: Alarm A flag
Note: The bits of this register are cleared 2 APB clock cycles after setting their corresponding
clear bit in the RTC_SCR register.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1.
This flag is set by hardware when a timestamp on the internal event occurs.
This flag is set by hardware when a timestamp event occurs while TSF is already set.
It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise,
an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit
is cleared.
This flag is set by hardware when a timestamp event occurs.
If ITSF flag is set, TSF must be cleared together with ITSF.
This flag is set by hardware when the wakeup auto-reload counter reaches 0.
If WUTOCLR[15:0] is different from 0x0000, WUTF is cleared by hardware when the wakeup
auto-reload counter reaches WUTOCLR value.
If WUTOCLR[15:0] is 0x0000, WUTF must be cleared by software.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
alarm B register (RTC_ALRMBR).
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
alarm A register (RTC_ALRMAR).
24 23 22
Res. Res. Res.
8 7 6
SSR
Res. Res.
UF
r
RM0453 Rev 2
Real-time clock (RTC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
ITSF TSOVF TSF WUTF
r r r r
17 16
Res. Res.
1 0
ALRBF ALRAF
r r
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