ST STM32WL55JC Reference Manual page 1051

RM0453
The following additional features are also available depending on the product
implementation (see
•
SMBus specification rev 3.0 compatibility:
–
–
–
–
–
–
• PMBus rev 1.3 standard compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
•
Wakeup from Stop mode on address match.
34.3 I2C implementation
The devices incorporate up to three I²C-bus controllers, I2C1, I2C2, and I2C3, with full or
limited feature sets as shown in the following table.
7-bit addressing mode
10-bit addressing mode
Standard-mode (up to 100 kbit/s)
Fast-mode (up to 400 kbit/s)
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
Independent clock
Wakeup from Stop mode
SMBus/PMBus
1. X = supported.
2. The register content is lost in Stop 2 mode.
3. Wakeup supported from Stop 0 and Stop 1 modes.
4. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.
34.4 I2C functional description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1 MHz) I
Section 34.3: I2C
Hardware PEC (packet error checking) generation and verification with ACK
control
Command and data acknowledge control
Address resolution protocol (ARP) support
Host and Device support
SMBus alert
Timeouts and idle condition detection
Table 222. STM32WL5x I2C implementation
I2C features
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
2
C bus.
Inter-integrated circuit (I2C) interface
implementation):
(1)
RM0453 Rev 2
(2) (2)
I2C1 I2C2
X X
X X
X X
X X
X X
X X
(3) (3)
X X
X X
1051/1454
I2C3
X
X
X
X
X
X
(4)
X
X
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