ST STM32WL55JC Reference Manual page 1044

Tamper and backup registers (TAMP)
Bit 21 ITAMP6IE: Internal tamper 6 interrupt enable
Bit 20 ITAMP5IE: Internal tamper 5 interrupt enable
Bit 19 Reserved, must be kept at reset value.
Bit 18 ITAMP3IE: Internal tamper 3 interrupt enable
Bit 17 Reserved, must be kept at reset value.
Bit 16 Reserved, must be kept at reset value.
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3IE: Tamper 3 interrupt enable
Bit 1 TAMP2IE: Tamper 2 interrupt enable
Bit 0 TAMP1IE: Tamper 1 interrupt enable
33.6.6 TAMP status register (TAMP_SR)
Address offset: 0x30
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 ITAMP8F: Internal tamper 8 flag
Bit 22 Reserved, must be kept at reset value.
1044/1454
0: Internal tamper 6 interrupt disabled.
1: Internal tamper 6 interrupt enabled.
0: Internal tamper 5 interrupt disabled.
1: Internal tamper 5 interrupt enabled.
0: Internal tamper 3 interrupt disabled.
1: Internal tamper 3 interrupt enabled.
0: Tamper 3 interrupt disabled.
1: Tamper 3 interrupt enabled..
0: Tamper 2 interrupt disabled.
1: Tamper 2 interrupt enabled.
0: Tamper 1 interrupt disabled.
1: Tamper 1 interrupt enabled.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This flag is set by hardware when a tamper detection event is detected on the internal
tamper 8.
24 23 22
ITAMP8 ITAMP6
Res. Res.
F
r
8 7 6
Res. Res. Res.
RM0453 Rev 2
21 20 19 18
ITAMP5 ITAMP3
Res.
F F F
r r r
5 4 3 2
TAMP
Res. Res. Res.
3F
r
RM0453
17 16
Res. Res.
1 0
TAMP TAMP
2F 1F
r r