Table 221. Tamp Register Map And Reset Values - ST STM32WL55JC Reference Manual

Inter-integrated circuit (I2C) interface
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).
If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also
available.
34.4.1 I2C block diagram
The block diagram of the I2C interface is shown in
i2c_ker_ck
i2c_pclk
The I2C is clocked by an independent clock source which allows the I2C to operate
independently from the PCLK frequency.
1052/1454
Figure 275. I2C block diagram
I2CCLK
Wakeup
on
address
match
PCLK
Figure
Data control
Digital
Shift register
noise
filter
SMBUS
PEC
generation/
check
Clock control
Master clock
Digital
generation
noise
Slave clock
filter
stretching
SMBus
Timeout
check
SMBus Alert
control/status
Registers
APB bus
RM0453 Rev 2
275.
Analog
noise
GPIO
filter
logic
Analog
noise
GPIO
filter
logic
RM0453
I2C_SDA
I2C_SCL
I2C_SMBA
MSv46198V2