Instructions That Disable Interrupts; Times When Interrupts Are Disabled; Interrupts During Execution Of Eepmov Instruction; Figure 5.7 Contention Between Interrupt Generation And Disabling - Hitachi H8S/2215 Series Hardware Manual

φ
Internal
address bus
Internal
write signal
TGIEA
TGFA
TGI0A
Interrupt signal

Figure 5.7 Contention between Interrupt Generation and Disabling

5.7.2

Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3

Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
5.7.4

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
Rev. 3.0, 10/02, page 96 of 686
TIER0 write cycle by CPU
TIER_0 address
TGI0A exception handling