Timing Of Tcnt External Reset; Figure 11.7 Timing Of Compare Match Clear; Figure 11.8 Timing Of Clearance By External Reset - Hitachi H8S/2215 Series Hardware Manual

ø
Compare match
signal
TCNT
11.5.5

Timing of TCNT External Reset

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 11.8
shows the timing of this operation.
ø
External reset
input pin
Clear signal
TCNT
N

Figure 11.7 Timing of Compare Match Clear

N–1

Figure 11.8 Timing of Clearance by External Reset

H'00
N H'00
Rev. 3.0, 10/02, page 337 of 686