Dma Control Register (Dmacr) - Hitachi H8S/2215 Series Hardware Manual

(b) ETCRB
ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is
decremented by 1 each time a block is transferred, and transfer ends when the count reaches
H'0000.
7.3.4

DMA Control Register (DMACR)

DMACR controls the operation of each DMAC channel.
• Short Address Mode (common to DMACRA and DMACRB)
Bit Bit Name Initial Value R/W
7 DTSZ 0
6 DTID 0
Description
R/W Data Transfer Size:
Selects the size of data to be transferred at one time.
0: Byte-size transfer
1: Word-size transfer
R/W Data Transfer Increment/Decrement:
Selects incrementing or decrementing of MAR every data
transfer in sequential mode or repeat mode.
In idle mode, MAR is neither incremented nor decremented.
0: MAR is incremented after a data transfer
•
When DTSZ = 0, MAR is incremented by 1 after a
transfer
•
When DTSZ = 1, MAR is incremented by 2 after a
transfer
1: MAR is decremented after a data transfer
•
When DTSZ = 0, MAR is decremented by 1 after a
transfer
•
When DTSZ = 1, MAR is decremented by 2 after a
transfer
Rev. 3.0, 10/02, page 147 of 686