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8.2
Register Descriptions ........................................................................................................ 197
8.2.1
DTC Mode Register A (MRA) ............................................................................ 197
8.2.2
DTC Mode Register B (MRB)............................................................................. 198
8.2.3
DTC Source Address Register (SAR).................................................................. 198
8.2.4
DTC Destination Address Register (DAR).......................................................... 198
8.2.5
DTC Transfer Count Register A (CRA) .............................................................. 198
8.2.6
DTC Transfer Count Register B (CRB)............................................................... 199
8.2.7
DTC Enable Registers (DTCERA to DTCERF).................................................. 199
8.2.8
DTC Vector Register (DTVECR)........................................................................ 200
8.3
Activation Sources ............................................................................................................ 201
8.4
Location of Register Information and DTC Vector Table ................................................ 202
8.5
Operation .......................................................................................................................... 205
8.5.1
Normal Mode....................................................................................................... 206
8.5.2
Repeat Mode ........................................................................................................ 208
8.5.3
Block Transfer Mode ........................................................................................... 209
8.5.4
Chain Transfer ..................................................................................................... 210
8.5.5
Interrupts.............................................................................................................. 211
8.5.6
Operation Timing................................................................................................. 211
8.5.7
Number of DTC Execution States ....................................................................... 212
8.6
Procedures for Using DTC................................................................................................ 214
8.6.1
Activation by Interrupt......................................................................................... 214
8.6.2
Activation by Software ........................................................................................ 214
8.7
Examples of Use of the DTC ............................................................................................ 215
8.7.1
Normal Mode....................................................................................................... 215
8.7.2
Software Activation ............................................................................................. 215
8.8
Usage Notes ...................................................................................................................... 216
8.8.1
Module Stop......................................................................................................... 216
8.8.2
On-Chip RAM ..................................................................................................... 216
8.8.3
DTCE Bit Setting................................................................................................. 216
8.8.4
DMAC Transfer End Interrupt............................................................................. 216
Section 9 I/O Ports .............................................................................................217
9.1
Port 1................................................................................................................................. 221
9.1.1
Port 1 Data Direction Register (P1DDR)............................................................. 221
9.1.2
Port 1 Data Register (P1DR)................................................................................ 221
9.1.3
Port 1 Register (PORT1)...................................................................................... 222
9.1.4
Pin Functions ....................................................................................................... 222
9.2
Port 3................................................................................................................................. 224
9.2.1
Port 3 Data Direction Register (P3DDR)............................................................. 225
9.2.2
Port 3 Data Register (P3DR)................................................................................ 225
9.2.3
Port 3 Register (PORT3)...................................................................................... 226
9.2.4
Port 3 Open-Drain Control Register (P3ODR) .................................................... 226
9.2.5
Pin Functions ....................................................................................................... 227
Rev. 3.0, 10/02, page xxxiii of lviii
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