System Clock Control Register (Sckcr); Module Stop Control Registers A To C (Mstpcra To Mstpcrc) - Hitachi H8S/2215 Series Hardware Manual

22.1.2

System Clock Control Register (SCKCR)

SCKCR performs ø clock output control and medium-speed mode control.
Bit Bit Name
7 PSTOP
6 —
5 —
4 —
3 —
2 SKC2
1 SCK1
0 SCK0
22.1.3

Module Stop Control Registers A to C (MSTPCRA to MSTPCRC)

MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.
Setting a bit to 1, causes the corresponding module to enter module stop mode, while clearing the
bit to 0 clears the module stop mode.
Rev. 3.0, 10/02, page 612 of 686
Initial Value R/W
0 R/W
0 R/W
0 —
0 —
0 R/W
0 R/W
0 R/W
0 R/W
Description
ø Clock Output Disable
This bit controls ø output.
0: Outputs ø clock in normal operating state and
sleep mode.
1: Fix ø clock high in normal operating state and
sleep mode.
For details, refer to section 22.7, ø Clock Output
Disabling Function.
Reserved:
This bit can be read from or written to but the write
value should always be 0.
Reserved:
These bits are always read as 0, and cannot be
modified.
Reserved:
This bit can be read from or written to but the write
value should always be 0.
System Clock Select 2 to 0:
These bits select the clock for the bus
master in high-speed mode and medium-speed
mode.
000: High-speed mode (ø)
001: Medium-speed mode (ø/2)
010: Medium-speed mode (ø/4)
011: Medium-speed mode (ø/8)
100: Medium-speed mode (ø/16)
101: Medium-speed mode (ø/32)
11x: Setting prohibited