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19.10
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI interrupt is disabled when flash memory is being programmed or
erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot
1
mode*
, to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
not be read correctly*
3. If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
Notes:*1 Interrupt requests must be disabled inside and outside the CPU until the programming
control program has completed programming.
*2 The vector may not be read correctly in this case for the following two reasons:
• If flash memory is read while being programmed or erased (while the P1 or E1 bit
is set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
• If the interrupt entry in the vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
19.11
Programmer Mode
In programmer mode, a PROM programmer can perform programming/erasing via a socket
adapter, just like for a discrete flash memory. Use a PROM programmer which supports the
Hitachi 256-kbyte flash memory on-chip MCU device type. Memory map in programmer mode is
shown in figure 19.13.
Rev. 3.0, 10/02, page 588 of 686
2
, possibly resulting in CPU runaway.
MCU mode
H'000000
On-chip ROM space
256 kbytes
H'03FFFF
Figure 19.13 Memory Map in Programmer Mode
Programmer mode
H'00000
H'3FFFF
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